[llvm] [RISCV][GISel] Custom promote s32 G_ROTL/ROTR on RV64. (PR #115107)

[Min-Yih Hsu via llvm-commits]

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@@ -203,8 +203,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
   getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();
 
   getActionDefinitionsBuilder({G_ROTL, G_ROTR})
-      .legalFor(ST.hasStdExtZbb() || ST.hasStdExtZbkb(),
-                {{s32, s32}, {sXLen, sXLen}})
+      .legalFor(ST.hasStdExtZbb() || ST.hasStdExtZbkb(), {{sXLen, sXLen}})
+      .customFor(ST.is64Bit() && (ST.hasStdExtZbb() || ST.hasStdExtZbkb()),
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mshockwave wrote:

nit: maybe factoring out `ST.hasStdExtZbb() || ST.hasStdExtZbkb()`?

https://github.com/llvm/llvm-project/pull/115107