[llvm] 200afcf - [RISCV] Add combines_for_extload to RISCVPostLegalizerCombiner.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-11-07T11:10:07-08:00
New Revision: 200afcf6128911892d61c2a331186fe9a4da2a3e

URL: https://github.com/llvm/llvm-project/commit/200afcf6128911892d61c2a331186fe9a4da2a3e
DIFF: https://github.com/llvm/llvm-project/commit/200afcf6128911892d61c2a331186fe9a4da2a3e.diff

LOG: [RISCV] Add combines_for_extload to RISCVPostLegalizerCombiner.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVCombine.td
    llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVCombine.td b/llvm/lib/Target/RISCV/RISCVCombine.td
index a2e67eef03561b..60d942957c8861 100644
--- a/llvm/lib/Target/RISCV/RISCVCombine.td
+++ b/llvm/lib/Target/RISCV/RISCVCombine.td
@@ -23,6 +23,6 @@ def RISCVO0PreLegalizerCombiner: GICombiner<
 // TODO: Add more combines.
 def RISCVPostLegalizerCombiner
     : GICombiner<"RISCVPostLegalizerCombinerImpl",
-                 [redundant_and, identity_combines, commute_constant_to_rhs,
-                  constant_fold_cast_op]> {
+                 [combines_for_extload, redundant_and, identity_combines,
+                  commute_constant_to_rhs, constant_fold_cast_op]> {
 }

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
index 77e57e6714d7ba..835b4e32ae3206 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
@@ -791,9 +791,7 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind {
 ;
 ; RV64ZBB-LABEL: ctpop_i32_load:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    lw a0, 0(a0)
-; RV64ZBB-NEXT:    slli a0, a0, 32
-; RV64ZBB-NEXT:    srli a0, a0, 32
+; RV64ZBB-NEXT:    lwu a0, 0(a0)
 ; RV64ZBB-NEXT:    cpopw a0, a0
 ; RV64ZBB-NEXT:    ret
   %a = load i32, ptr %p