[llvm] [RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on RV64. (PR #115101)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 7 09:22:48 PST 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/115101
>From 1574ca53ccce0edbb7e5f91edbf697a349db57d7 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 17 Oct 2024 11:14:54 -0700
Subject: [PATCH] [RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on
RV64.
I plan to make i32 an illegal type for RV64 to match SelectionDAG
and to remove i32 from the GPR register class.
I've added 2 custom nodes for CTZW and CLZW to match SelectionDAG.
The cpopw regressions will be fixed by #115097.
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 28 ++++++++--
llvm/lib/Target/RISCV/RISCVGISel.td | 4 --
llvm/lib/Target/RISCV/RISCVInstrGISel.td | 16 ++++++
.../instruction-select/ctlz-rv64.mir | 6 +--
.../instruction-select/ctpop-rv64.mir | 19 -------
.../instruction-select/cttz-rv64.mir | 6 +--
.../legalizer/legalize-ctlz-rv64.mir | 52 +++++++++----------
.../legalizer/legalize-ctpop-rv64.mir | 33 ++++++------
.../legalizer/legalize-cttz-rv64.mir | 40 ++++++--------
llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll | 10 ++--
10 files changed, 106 insertions(+), 108 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index f2a51a7ea0d426..1f55341992021d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -224,7 +224,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
auto &CountZerosUndefActions =
getActionDefinitionsBuilder({G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF});
if (ST.hasStdExtZbb()) {
- CountZerosActions.legalFor({{s32, s32}, {sXLen, sXLen}})
+ CountZerosActions.legalFor({{sXLen, sXLen}})
+ .customFor({{s32, s32}})
.clampScalar(0, s32, sXLen)
.widenScalarToNextPow2(0)
.scalarSameSizeAs(1, 0);
@@ -236,9 +237,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
auto &CTPOPActions = getActionDefinitionsBuilder(G_CTPOP);
if (ST.hasStdExtZbb()) {
- CTPOPActions.legalFor({{s32, s32}, {sXLen, sXLen}})
- .clampScalar(0, s32, sXLen)
- .widenScalarToNextPow2(0)
+ CTPOPActions.legalFor({{sXLen, sXLen}})
+ .clampScalar(0, sXLen, sXLen)
.scalarSameSizeAs(1, 0);
} else {
CTPOPActions.maxScalar(0, sXLen).scalarSameSizeAs(1, 0).lower();
@@ -1154,6 +1154,17 @@ bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
return true;
}
+static unsigned getRISCVWOpcode(unsigned Opcode) {
+ switch (Opcode) {
+ default:
+ llvm_unreachable("Unexpected opcode");
+ case TargetOpcode::G_CTLZ:
+ return RISCV::G_CLZW;
+ case TargetOpcode::G_CTTZ:
+ return RISCV::G_CTZW;
+ }
+}
+
bool RISCVLegalizerInfo::legalizeCustom(
LegalizerHelper &Helper, MachineInstr &MI,
LostDebugLocObserver &LocObserver) const {
@@ -1190,6 +1201,15 @@ bool RISCVLegalizerInfo::legalizeCustom(
return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==
LegalizerHelper::Legalized;
}
+ case TargetOpcode::G_CTLZ:
+ case TargetOpcode::G_CTTZ: {
+ Helper.Observer.changingInstr(MI);
+ Helper.widenScalarSrc(MI, sXLen, 1, TargetOpcode::G_ANYEXT);
+ Helper.widenScalarDst(MI, sXLen);
+ MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode())));
+ Helper.Observer.changedInstr(MI);
+ return true;
+ }
case TargetOpcode::G_IS_FPCLASS: {
Register GISFPCLASS = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 40aae220fbd47e..8ed6887b04ba3c 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -248,10 +248,6 @@ def : PatGprGpr<urem, REMUW, i32, i32>;
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZbb, IsRV64] in {
-def : PatGpr<ctlz, CLZW, i32>;
-def : PatGpr<cttz, CTZW, i32>;
-def : PatGpr<ctpop, CPOPW, i32>;
-
def : Pat<(i32 (sext_inreg GPR:$rs1, i8)), (SEXT_B GPR:$rs1)>;
def : Pat<(i32 (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrGISel.td b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
index 763aead84dd8f4..927811eef6618b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
@@ -17,6 +17,22 @@ class RISCVGenericInstruction : GenericInstruction {
let Namespace = "RISCV";
}
+// Pseudo equivalent to a RISCVISD::CLZW.
+def G_CLZW : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_CLZW, riscv_clzw>;
+
+// Pseudo equivalent to a RISCVISD::CTZW.
+def G_CTZW : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_CTZW, riscv_ctzw>;
+
// Pseudo equivalent to a RISCVISD::FCLASS.
def G_FCLASS : RISCVGenericInstruction {
let OutOperandList = (outs type0:$dst);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir
index 8c75bdd38d732a..f6e04a9999dbf8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir
@@ -15,10 +15,8 @@ body: |
; RV64I-NEXT: $x10 = COPY [[CLZW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0
- %2:gprb(s32) = G_CTLZ %1
- %3:gprb(s64) = G_ANYEXT %2
- $x10 = COPY %3(s64)
+ %1:gprb(s64) = G_CLZW %0
+ $x10 = COPY %1(s64)
PseudoRET implicit $x10
...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv64.mir
index 7d584a8589b901..f91f029209220f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv64.mir
@@ -3,25 +3,6 @@
# RUN: -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64I %s
----
-name: ctpop_s32
-legalized: true
-regBankSelected: true
-body: |
- bb.0.entry:
- ; RV64I-LABEL: name: ctpop_s32
- ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; RV64I-NEXT: [[CPOPW:%[0-9]+]]:gpr = CPOPW [[COPY]]
- ; RV64I-NEXT: $x10 = COPY [[CPOPW]]
- ; RV64I-NEXT: PseudoRET implicit $x10
- %0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0
- %2:gprb(s32) = G_CTPOP %1
- %3:gprb(s64) = G_ANYEXT %2
- $x10 = COPY %3(s64)
- PseudoRET implicit $x10
-
-...
---
name: ctpop_s64
legalized: true
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir
index b56d45f0993ada..17fb381da6cdbb 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir
@@ -15,10 +15,8 @@ body: |
; RV64I-NEXT: $x10 = COPY [[CTZW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0
- %2:gprb(s32) = G_CTTZ %1
- %3:gprb(s64) = G_ANYEXT %2
- $x10 = COPY %3(s64)
+ %1:gprb(s64) = G_CTZW %0
+ $x10 = COPY %1(s64)
PseudoRET implicit $x10
...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
index bc6aafb1e3b2cc..f4ea4f5eb43aa3 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
@@ -57,12 +57,12 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]]
+ ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CLZW]](s64)
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]]
+ ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C1]]
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -133,12 +133,12 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]]
+ ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CLZW]](s64)
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]]
+ ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C1]]
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -204,10 +204,8 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[TRUNC]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CTLZ]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[COPY]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[CLZW]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
@@ -333,12 +331,12 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]]
+ ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CLZW]](s64)
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]]
+ ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C1]]
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -409,12 +407,12 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]]
+ ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CLZW]](s64)
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]]
+ ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C1]]
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -480,10 +478,8 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[TRUNC]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CTLZ]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[COPY]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[CLZW]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
index ec885c170b5b60..48595dc9809c74 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
@@ -46,13 +46,11 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
- ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64)
+ ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64)
+ ; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s8) = G_TRUNC %1(s64)
@@ -106,13 +104,11 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
- ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64)
+ ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64)
+ ; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %1(s64)
@@ -161,10 +157,11 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[TRUNC]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CTPOP]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64)
+ ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64)
+ ; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
index f8285d609875ba..c3b6d357d241d7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
@@ -52,10 +52,9 @@ body: |
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[C]]
- ; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
- ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
+ ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[ANYEXT]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s8) = G_TRUNC %1(s64)
@@ -115,10 +114,9 @@ body: |
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[C]]
- ; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
- ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
+ ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[ANYEXT]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %1(s64)
@@ -171,10 +169,8 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[TRUNC]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CTTZ]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[COPY]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
@@ -282,10 +278,9 @@ body: |
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[C]]
- ; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
- ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
+ ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[ANYEXT]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s8) = G_TRUNC %1(s64)
@@ -345,10 +340,9 @@ body: |
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[C]]
- ; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
- ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
+ ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[ANYEXT]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %1(s64)
@@ -401,10 +395,8 @@ body: |
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[TRUNC]](s32)
- ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CTTZ]](s32)
- ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[COPY]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
index 7b805f17488250..f6cea2119ebe86 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
@@ -733,7 +733,9 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind {
;
; RV64ZBB-LABEL: ctpop_i32:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: cpopw a0, a0
+; RV64ZBB-NEXT: slli a0, a0, 32
+; RV64ZBB-NEXT: srli a0, a0, 32
+; RV64ZBB-NEXT: cpop a0, a0
; RV64ZBB-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %1
@@ -779,9 +781,9 @@ define i1 @ctpop_i32_ult_two(i32 signext %a) nounwind {
; RV64ZBB-LABEL: ctpop_i32_ult_two:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: li a1, 2
-; RV64ZBB-NEXT: cpopw a0, a0
; RV64ZBB-NEXT: slli a0, a0, 32
; RV64ZBB-NEXT: srli a0, a0, 32
+; RV64ZBB-NEXT: cpop a0, a0
; RV64ZBB-NEXT: slli a1, a1, 32
; RV64ZBB-NEXT: srli a1, a1, 32
; RV64ZBB-NEXT: sltu a0, a0, a1
@@ -824,7 +826,9 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind {
; RV64ZBB-LABEL: ctpop_i32_load:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lw a0, 0(a0)
-; RV64ZBB-NEXT: cpopw a0, a0
+; RV64ZBB-NEXT: slli a0, a0, 32
+; RV64ZBB-NEXT: srli a0, a0, 32
+; RV64ZBB-NEXT: cpop a0, a0
; RV64ZBB-NEXT: ret
%a = load i32, ptr %p
%1 = call i32 @llvm.ctpop.i32(i32 %a)
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