[llvm] 79fd615 - [SLP][NFC]Add a test with the segmented loads, NFC

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2024-11-07T07:08:24-08:00
New Revision: 79fd61575977cb792af66b442fc2c6fbe837ebe4

URL: https://github.com/llvm/llvm-project/commit/79fd61575977cb792af66b442fc2c6fbe837ebe4
DIFF: https://github.com/llvm/llvm-project/commit/79fd61575977cb792af66b442fc2c6fbe837ebe4.diff

LOG: [SLP][NFC]Add a test with the segmented loads, NFC

Added: 
    llvm/test/Transforms/SLPVectorizer/RISCV/segmented-stores.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Transforms/SLPVectorizer/RISCV/segmented-stores.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/segmented-stores.ll
new file mode 100644
index 00000000000000..ae1c3e1ee0da20
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/segmented-stores.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux -mattr=+v -pass-remarks-output=%t -mcpu=sifive-p670 < %s | FileCheck %s
+; RUN: FileCheck %s --check-prefix YAML --input-file=%t
+
+; YAML-LABEL: --- !Passed
+; YAML-NEXT: Pass:            slp-vectorizer
+; YAML-NEXT: Name:            StoresVectorized
+; YAML-NEXT: Function:        test
+; YAML-NEXT: Args:
+; YAML-NEXT:   - String:          'Stores SLP vectorized with cost '
+; YAML-NEXT:   - Cost:            '-1'
+; YAML-NEXT:   - String:          ' and with tree size '
+; YAML-NEXT:   - TreeSize:        '2'
+define void @test(ptr %h) {
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: ptr [[H:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[DCT2X211:%.*]] = alloca [0 x [0 x [8 x i64]]], i32 0, align 16
+; CHECK-NEXT:    [[CHROMA_DC209:%.*]] = getelementptr i8, ptr [[H]], i64 0
+; CHECK-NEXT:    [[ARRAYIDX33_I:%.*]] = getelementptr i8, ptr [[DCT2X211]], i64 8
+; CHECK-NEXT:    [[ARRAYIDX36_I181:%.*]] = getelementptr i8, ptr [[DCT2X211]], i64 24
+; CHECK-NEXT:    [[TMP0:%.*]] = call <2 x i64> @llvm.experimental.vp.strided.load.v2i64.p0.i64(ptr align 4 [[DCT2X211]], i64 16, <2 x i1> splat (i1 true), i32 2)
+; CHECK-NEXT:    store <2 x i64> [[TMP0]], ptr [[CHROMA_DC209]], align 2
+; CHECK-NEXT:    [[TMP2:%.*]] = load i64, ptr [[ARRAYIDX33_I]], align 2
+; CHECK-NEXT:    [[ARRAYIDX5_I226:%.*]] = getelementptr i8, ptr [[H]], i64 16
+; CHECK-NEXT:    store i64 [[TMP2]], ptr [[ARRAYIDX5_I226]], align 2
+; CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr [[ARRAYIDX36_I181]], align 2
+; CHECK-NEXT:    [[ARRAYIDX7_I228:%.*]] = getelementptr i8, ptr [[H]], i64 24
+; CHECK-NEXT:    store i64 [[TMP3]], ptr [[ARRAYIDX7_I228]], align 2
+; CHECK-NEXT:    ret void
+;
+entry:
+  %dct2x211 = alloca [0 x [0 x [8 x i64]]], i32 0, align 16
+  %chroma_dc209 = getelementptr i8, ptr %h, i64 0
+  %arrayidx30.i = getelementptr i8, ptr %dct2x211, i64 16
+  %arrayidx33.i = getelementptr i8, ptr %dct2x211, i64 8
+  %arrayidx36.i181 = getelementptr i8, ptr %dct2x211, i64 24
+  %0 = load i64, ptr %dct2x211, align 16
+  store i64 %0, ptr %chroma_dc209, align 2
+  %1 = load i64, ptr %arrayidx30.i, align 4
+  %arrayidx3.i224 = getelementptr i8, ptr %h, i64 8
+  store i64 %1, ptr %arrayidx3.i224, align 2
+  %2 = load i64, ptr %arrayidx33.i, align 2
+  %arrayidx5.i226 = getelementptr i8, ptr %h, i64 16
+  store i64 %2, ptr %arrayidx5.i226, align 2
+  %3 = load i64, ptr %arrayidx36.i181, align 2
+  %arrayidx7.i228 = getelementptr i8, ptr %h, i64 24
+  store i64 %3, ptr %arrayidx7.i228, align 2
+  ret void
+}
+