[llvm] [AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes (PR #115291)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-dev-x86-64` running on `ml-opt-dev-x86-64-b1` while building `llvm` at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/137/builds/8204

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 1: /b/ml-opt-dev-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll -o - | /b/ml-opt-dev-x86-64-b1/build/bin/FileCheck /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
+ /b/ml-opt-dev-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll -o -
+ /b/ml-opt-dev-x86-64-b1/build/bin/FileCheck /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
/b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll:42:15: error: CHECK-NEXT: is not on the line after the previous match
; CHECK-NEXT: vgprForAGPRCopy: ''
              ^
<stdin>:151:2: note: 'next' match was here
 vgprForAGPRCopy: ''
 ^
<stdin>:149:14: note: previous match ended here
 occupancy: 8
             ^
<stdin>:150:1: note: non-matching line after previous match is here
 numPhysicalVGPRSpillLanes: 0
^

Input file: <stdin>
Check file: /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
         .
         .
         .
       146:  fp64-fp16-input-denormals: true 
       147:  fp64-fp16-output-denormals: true 
       148:  highBitsOf32BitAddress: 0 
       149:  occupancy: 8 
       150:  numPhysicalVGPRSpillLanes: 0 
       151:  vgprForAGPRCopy: '' 
next:42      !~~~~~~~~~~~~~~~~~~  error: match on wrong line
       152:  sgprForEXECCopy: '$sgpr100_sgpr101' 
       153:  longBranchReservedReg: '$sgpr2_sgpr3' 
       154:  hasInitWholeWave: false 
       155: body: | 
       156:  bb.0.bb0: 
         .
         .
         .
>>>>>>

--

...

```

</details>

https://github.com/llvm/llvm-project/pull/115291