[llvm] [RISCV][AsmParser] Allow parsing vset{i}vli omitting LMUL parameter (PR #115277)

[Aleksei Romanov via llvm-commits]

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@@ -2320,7 +2326,7 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
   return Error(
       ErrorLoc,
       "operand must be "
-      "e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
+      "e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}");
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saveasguy wrote:

IMHO, it's better to stick with the current changes since looks like RVV 1.0 doesn't support optional mask/tail policies, and someone who is interested in compatibility with the RVV 0.7.1 can do changes above this PR.
Anyway, I would like to hear your opinion on this.

https://github.com/llvm/llvm-project/pull/115277