[llvm] [RISCV][AsmParser] Allow parsing vsetvl omitting LMUL parameter (PR #115277)

[Aleksei Romanov via llvm-commits]

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@@ -2320,7 +2326,7 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
   return Error(
       ErrorLoc,
       "operand must be "
-      "e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
+      "e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}");
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saveasguy wrote:

1. https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp#L1651 -- here `[` means optional so you're right that original format is not right. This is why I've changed `[` to `{`.
2. As far as I can see from RISC-V spec mask/tail policies are not optional. GCC also doesn't think so: https://godbolt.org/z/54h1Kf3a1

https://github.com/llvm/llvm-project/pull/115277