[llvm] d87dbcb - [LoongArch] Reuse GPRRegisterClass to shorten some code in LoongArchRegisterInfo.td. NFC

[via llvm-commits]

Author: wanglei
Date: 2024-11-07T19:30:35+08:00
New Revision: d87dbcbf137ab1c6b6c2db1fd3fe7d91a3142fa1

URL: https://github.com/llvm/llvm-project/commit/d87dbcbf137ab1c6b6c2db1fd3fe7d91a3142fa1
DIFF: https://github.com/llvm/llvm-project/commit/d87dbcbf137ab1c6b6c2db1fd3fe7d91a3142fa1.diff

LOG: [LoongArch] Reuse GPRRegisterClass to shorten some code in LoongArchRegisterInfo.td. NFC

Added: 
    

Modified: 
    llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
index fbca110fd09305..2d3a7c364f0bf4 100644
--- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
@@ -97,32 +97,29 @@ def GRLenRI : RegInfoByHwMode<
       [LA32,              LA64],
       [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
 
-// The order of registers represents the preferred allocation sequence.
-// Registers are listed in the order caller-save, callee-save, specials.
-def GPR : RegisterClass<"LoongArch", [GRLenVT], 32, (add
-    // Argument registers (a0...a7)
-    (sequence "R%u", 4, 11),
-    // Temporary registers (t0...t8)
-    (sequence "R%u", 12, 20),
-    // Static register (s9/fp, s0...s8)
-    (sequence "R%u", 22, 31),
-    // Specials (r0, ra, tp, sp)
-    (sequence "R%u", 0, 3),
-    // Reserved (Non-allocatable)
-    R21
-  )> {
+class GPRRegisterClass<dag regList>
+    : RegisterClass<"LoongArch", [GRLenVT], 32, regList> {
   let RegInfos = GRLenRI;
 }
 
+// The order of registers represents the preferred allocation sequence.
+// Registers are listed in the order caller-save, callee-save, specials.
+def GPR : GPRRegisterClass<(add // Argument registers (a0...a7)
+                                (sequence "R%u", 4, 11),
+                                // Temporary registers (t0...t8)
+                                (sequence "R%u", 12, 20),
+                                // Static register (s9/fp, s0...s8)
+                                (sequence "R%u", 22, 31),
+                                // Specials (r0, ra, tp, sp)
+                                (sequence "R%u", 0, 3),
+                                // Reserved (Non-allocatable)
+                                R21)>;
+
 // GPR for indirect tail calls. We can't use callee-saved registers, as they are
 // restored to the saved value before the tail call, which would clobber a call
 // address.
-def GPRT : RegisterClass<"LoongArch", [GRLenVT], 32, (add
-    // a0...a7, t0...t8
-    (sequence "R%u", 4, 20)
-  )> {
-  let RegInfos = GRLenRI;
-}
+def GPRT : GPRRegisterClass<(add // a0...a7, t0...t8
+                                 (sequence "R%u", 4, 20))>;
 
 // Floating point registers