[llvm] [AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes (PR #115291)

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git-clang-format --diff bf01bb851b1e1a977ba1b92e7eb9c8c6d773e6d5 6c29b994ac483648a0c1876d587c92effc5f46d7 --extensions h,cpp -- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 6cd4a449de..db4aefadae 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -338,7 +338,8 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
     YamlIO.mapOptional("highBitsOf32BitAddress",
                        MFI.HighBitsOf32BitAddress, 0u);
     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
-    YamlIO.mapOptional("numPhysicalVGPRSpillLanes", MFI.NumPhysicalVGPRSpillLanes);
+    YamlIO.mapOptional("numPhysicalVGPRSpillLanes",
+                       MFI.NumPhysicalVGPRSpillLanes);
     YamlIO.mapOptional("spillPhysVGPRs", MFI.SpillPhysVGPRS);
     YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
     YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
@@ -616,7 +617,9 @@ public:
   ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
   ArrayRef<Register> getSGPRSpillPhysVGPRs() const { return SpillPhysVGPRs; }
 
-  unsigned getNumPhysicalVGPRSpillLanes() const { return NumPhysicalVGPRSpillLanes; }
+  unsigned getNumPhysicalVGPRSpillLanes() const {
+    return NumPhysicalVGPRSpillLanes;
+  }
 
   const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }
   const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }

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https://github.com/llvm/llvm-project/pull/115291