[llvm] [RISCV][AsmParser] Allow parsing vsetvl omitting LMUL parameter (PR #115277)

via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 7 00:24:57 PST 2024 

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Aleksei Romanov (saveasguy)

<details>
<summary>Changes</summary>

>From RISC-V Unprivileged Specification version 20240411 (https://github.com/riscv/riscv-isa-manual/releases/tag/20240411) , paragraph 31.6, it's valid to omit LMUL parameter.
GCC has already supported it: https://godbolt.org/z/YxnEK3aer.
So this patch introduces support of such behavior. 

---
Full diff: https://github.com/llvm/llvm-project/pull/115277.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+9-3) 
- (modified) llvm/test/MC/RISCV/rvv/invalid.s (+30-30) 
- (modified) llvm/test/MC/RISCV/rvv/vsetvl.s (+7) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 4d46afb8c4ef97..77d527c4fafe3f 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2222,8 +2222,14 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State,
     State = VTypeState_LMUL;
     return false;
   case VTypeState_LMUL: {
-    if (!Identifier.consume_front("m"))
-      break;
+    // Set LMUL to default if it is omitted.
+    if (!Identifier.consume_front("m")) {
+      Lmul = 1;
+      Fractional = false;
+      State = VTypeState_TailPolicy;
+      return parseVTypeToken(Tok, State, Sew, Lmul, Fractional, TailAgnostic,
+                             MaskAgnostic);
+    }
     Fractional = Identifier.consume_front("f");
     if (Identifier.getAsInteger(10, Lmul))
       break;
@@ -2320,7 +2326,7 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
   return Error(
       ErrorLoc,
       "operand must be "
-      "e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
+      "e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}");
 }
 
 ParseStatus RISCVAsmParser::parseMaskReg(OperandVector &Operands) {
diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s
index 07e7b9db6606c5..5bee95f4a1f1c7 100644
--- a/llvm/test/MC/RISCV/rvv/invalid.s
+++ b/llvm/test/MC/RISCV/rvv/invalid.s
@@ -2,95 +2,95 @@
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 
 vsetivli a2, 32, e8,m1
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetivli a2, zero, e8,m1
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetivli a2, 5, (1 << 10)
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetivli a2, 5, 0x400
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetivli a2, 5, e31
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, (1 << 11)
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, 0x800
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 
 vsetvli a2, a0, e31
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e32,m3
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, m1,e32
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e32,m16
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e128,m8
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e256,m8
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e512,m8
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e1024,m8
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e2048,m8
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e1,m8
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,m1,tx
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,m1,ta,mx
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,m1,ma
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,m1,mu
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8x,m1,tu,mu
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,m1z,tu,mu
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,mf1,tu,mu
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,m1,tu,mut
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,m1,tut,mu
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,m1
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,m1,ta
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vsetvli a2, a0, e8,1,ta,ma
-# CHECK-ERROR: operand must be e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e{8|16|32|64},[m{1|2|4|8|f2|f4|f8},]{ta|tu},{ma|mu}
 
 vadd.vv v1, v3, v2, v4.t
 # CHECK-ERROR: operand must be v0.t
diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s
index 2741def0eeff21..37e763c24cde15 100644
--- a/llvm/test/MC/RISCV/rvv/vsetvl.s
+++ b/llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -10,6 +10,13 @@
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v %s \
 # RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
+# LMUL is omitted.
+vsetvli a2, a0, e8, ta, ma
+# CHECK-INST: vsetvli a2, a0, e8, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x05,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+# CHECK-UNKNOWN: 0c057657 <unknown>
+
 # reserved filed: vlmul[2:0]=4, vsew[2:0]=0b1xx, non-zero bits 8/9/10.
 vsetvli a2, a0, 0x224
 # CHECK-INST: vsetvli a2, a0, 548

``````````

</details>


https://github.com/llvm/llvm-project/pull/115277

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