[llvm] [RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (PR #115236)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 6 20:31:16 PST 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/115236
>From f9ac14730d6683f43c9a4b6ed77aa5d792f83a46 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 17 Oct 2024 17:02:09 -0700
Subject: [PATCH 1/2] [RISCV][GISel] Remove s32 input support for
G_SITOFP/UITOFP on RV64.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 24 ++++
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 4 +-
llvm/lib/Target/RISCV/RISCVGISel.td | 3 +
.../RISCV/GlobalISel/double-convert.ll | 92 +++++++++-----
.../CodeGen/RISCV/GlobalISel/float-convert.ll | 92 +++++++++-----
.../instruction-select/itofp-f16-rv64.mir | 46 -------
.../instruction-select/itofp-rv64.mir | 92 --------------
.../legalizer/legalize-itofp-f16-rv64.mir | 57 ++++-----
.../legalizer/legalize-itofp-rv64.mir | 114 ++++++++----------
.../regbankselect/itofp-f16-rv64.mir | 46 -------
.../GlobalISel/regbankselect/itofp-rv64.mir | 92 --------------
11 files changed, 235 insertions(+), 427 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index bc718b454ffb69..02ccd7e6bd48dd 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -87,6 +87,12 @@ class RISCVInstructionSelector : public InstructionSelector {
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const;
+ ComplexRendererFns selectSExtBits(MachineOperand &Root, unsigned Bits) const;
+ template <unsigned Bits>
+ ComplexRendererFns selectSExtBits(MachineOperand &Root) const {
+ return selectSExtBits(Root, Bits);
+ }
+
ComplexRendererFns selectZExtBits(MachineOperand &Root, unsigned Bits) const;
template <unsigned Bits>
ComplexRendererFns selectZExtBits(MachineOperand &Root) const {
@@ -248,6 +254,24 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const {
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(ShAmtReg); }}};
}
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectSExtBits(MachineOperand &Root,
+ unsigned Bits) const {
+ if (!Root.isReg())
+ return std::nullopt;
+ MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
+
+ if (RootDef->getOpcode() == TargetOpcode::G_SEXT_INREG &&
+ RootDef->getOperand(2).getImm() == Bits) {
+ return {
+ {[=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); }}};
+ }
+
+ // TODO: Use computeNumSignBits.
+
+ return std::nullopt;
+}
+
InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::selectZExtBits(MachineOperand &Root,
unsigned Bits) const {
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 34742394a291ed..3f8b09efc0c689 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -541,9 +541,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.libcallFor(ST.is64Bit(), {{s128, s32}, {s128, s64}});
getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
- .legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {s32, sXLen})))
+ .legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {sXLen})))
.widenScalarToNextPow2(1)
- .minScalar(1, s32)
+ .minScalar(1, sXLen)
.libcallFor({{s32, s32}, {s64, s32}, {s32, s64}, {s64, s64}})
.libcallFor(ST.is64Bit(), {{s32, s128}, {s64, s128}});
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 36881b02da2e40..57ab55169e4a68 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -96,6 +96,9 @@ def gi_sh2add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<2>">,
def gi_sh3add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<3>">,
GIComplexPatternEquiv<sh3add_uw_op>;
+def gi_sexti32 : GIComplexOperandMatcher<s64, "selectSExtBits<32>">,
+ GIComplexPatternEquiv<sexti32>;
+
def gi_zexti32 : GIComplexOperandMatcher<s64, "selectZExtBits<32>">,
GIComplexPatternEquiv<zexti32>;
def gi_zexti16 : GIComplexOperandMatcher<s32, "selectZExtBits<16>">,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
index 785cc2aafde11b..203b9c53de9d25 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
@@ -78,11 +78,17 @@ define double @fcvt_d_w(i32 %a) nounwind {
}
define double @fcvt_d_w_load(ptr %p) nounwind {
-; CHECKIFD-LABEL: fcvt_d_w_load:
-; CHECKIFD: # %bb.0:
-; CHECKIFD-NEXT: lw a0, 0(a0)
-; CHECKIFD-NEXT: fcvt.d.w fa0, a0
-; CHECKIFD-NEXT: ret
+; RV32IFD-LABEL: fcvt_d_w_load:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: lw a0, 0(a0)
+; RV32IFD-NEXT: fcvt.d.w fa0, a0
+; RV32IFD-NEXT: ret
+;
+; RV64IFD-LABEL: fcvt_d_w_load:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: lw a0, 0(a0)
+; RV64IFD-NEXT: fcvt.d.l fa0, a0
+; RV64IFD-NEXT: ret
%a = load i32, ptr %p
%1 = sitofp i32 %a to double
ret double %1
@@ -98,11 +104,19 @@ define double @fcvt_d_wu(i32 %a) nounwind {
}
define double @fcvt_d_wu_load(ptr %p) nounwind {
-; CHECKIFD-LABEL: fcvt_d_wu_load:
-; CHECKIFD: # %bb.0:
-; CHECKIFD-NEXT: lw a0, 0(a0)
-; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
-; CHECKIFD-NEXT: ret
+; RV32IFD-LABEL: fcvt_d_wu_load:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: lw a0, 0(a0)
+; RV32IFD-NEXT: fcvt.d.wu fa0, a0
+; RV32IFD-NEXT: ret
+;
+; RV64IFD-LABEL: fcvt_d_wu_load:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: lw a0, 0(a0)
+; RV64IFD-NEXT: slli a0, a0, 32
+; RV64IFD-NEXT: srli a0, a0, 32
+; RV64IFD-NEXT: fcvt.d.lu fa0, a0
+; RV64IFD-NEXT: ret
%a = load i32, ptr %p
%1 = uitofp i32 %a to double
ret double %1
@@ -228,37 +242,57 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind {
}
define double @fcvt_d_w_i8(i8 signext %a) nounwind {
-; CHECKIFD-LABEL: fcvt_d_w_i8:
-; CHECKIFD: # %bb.0:
-; CHECKIFD-NEXT: fcvt.d.w fa0, a0
-; CHECKIFD-NEXT: ret
+; RV32IFD-LABEL: fcvt_d_w_i8:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: fcvt.d.w fa0, a0
+; RV32IFD-NEXT: ret
+;
+; RV64IFD-LABEL: fcvt_d_w_i8:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fcvt.d.l fa0, a0
+; RV64IFD-NEXT: ret
%1 = sitofp i8 %a to double
ret double %1
}
define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
-; CHECKIFD-LABEL: fcvt_d_wu_i8:
-; CHECKIFD: # %bb.0:
-; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
-; CHECKIFD-NEXT: ret
+; RV32IFD-LABEL: fcvt_d_wu_i8:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: fcvt.d.wu fa0, a0
+; RV32IFD-NEXT: ret
+;
+; RV64IFD-LABEL: fcvt_d_wu_i8:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fcvt.d.lu fa0, a0
+; RV64IFD-NEXT: ret
%1 = uitofp i8 %a to double
ret double %1
}
define double @fcvt_d_w_i16(i16 signext %a) nounwind {
-; CHECKIFD-LABEL: fcvt_d_w_i16:
-; CHECKIFD: # %bb.0:
-; CHECKIFD-NEXT: fcvt.d.w fa0, a0
-; CHECKIFD-NEXT: ret
+; RV32IFD-LABEL: fcvt_d_w_i16:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: fcvt.d.w fa0, a0
+; RV32IFD-NEXT: ret
+;
+; RV64IFD-LABEL: fcvt_d_w_i16:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fcvt.d.l fa0, a0
+; RV64IFD-NEXT: ret
%1 = sitofp i16 %a to double
ret double %1
}
define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
-; CHECKIFD-LABEL: fcvt_d_wu_i16:
-; CHECKIFD: # %bb.0:
-; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
-; CHECKIFD-NEXT: ret
+; RV32IFD-LABEL: fcvt_d_wu_i16:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: fcvt.d.wu fa0, a0
+; RV32IFD-NEXT: ret
+;
+; RV64IFD-LABEL: fcvt_d_wu_i16:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fcvt.d.lu fa0, a0
+; RV64IFD-NEXT: ret
%1 = uitofp i16 %a to double
ret double %1
}
@@ -274,7 +308,7 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1
-; RV64IFD-NEXT: fcvt.d.w fa5, a0
+; RV64IFD-NEXT: fcvt.d.l fa5, a0
; RV64IFD-NEXT: fsd fa5, 0(a1)
; RV64IFD-NEXT: ret
%3 = add i32 %0, 1
@@ -294,7 +328,9 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1
-; RV64IFD-NEXT: fcvt.d.wu fa5, a0
+; RV64IFD-NEXT: slli a2, a0, 32
+; RV64IFD-NEXT: srli a2, a2, 32
+; RV64IFD-NEXT: fcvt.d.lu fa5, a2
; RV64IFD-NEXT: fsd fa5, 0(a1)
; RV64IFD-NEXT: ret
%3 = add i32 %0, 1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
index d6a36c5a702ac8..5d0206359af385 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
@@ -81,11 +81,17 @@ define float @fcvt_s_w(i32 %a) nounwind {
}
define float @fcvt_s_w_load(ptr %p) nounwind {
-; CHECKIF-LABEL: fcvt_s_w_load:
-; CHECKIF: # %bb.0:
-; CHECKIF-NEXT: lw a0, 0(a0)
-; CHECKIF-NEXT: fcvt.s.w fa0, a0
-; CHECKIF-NEXT: ret
+; RV32IF-LABEL: fcvt_s_w_load:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: lw a0, 0(a0)
+; RV32IF-NEXT: fcvt.s.w fa0, a0
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_w_load:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: lw a0, 0(a0)
+; RV64IF-NEXT: fcvt.s.l fa0, a0
+; RV64IF-NEXT: ret
%a = load i32, ptr %p
%1 = sitofp i32 %a to float
ret float %1
@@ -101,11 +107,19 @@ define float @fcvt_s_wu(i32 %a) nounwind {
}
define float @fcvt_s_wu_load(ptr %p) nounwind {
-; CHECKIF-LABEL: fcvt_s_wu_load:
-; CHECKIF: # %bb.0:
-; CHECKIF-NEXT: lw a0, 0(a0)
-; CHECKIF-NEXT: fcvt.s.wu fa0, a0
-; CHECKIF-NEXT: ret
+; RV32IF-LABEL: fcvt_s_wu_load:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: lw a0, 0(a0)
+; RV32IF-NEXT: fcvt.s.wu fa0, a0
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_wu_load:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: lw a0, 0(a0)
+; RV64IF-NEXT: slli a0, a0, 32
+; RV64IF-NEXT: srli a0, a0, 32
+; RV64IF-NEXT: fcvt.s.lu fa0, a0
+; RV64IF-NEXT: ret
%a = load i32, ptr %p
%1 = uitofp i32 %a to float
ret float %1
@@ -198,37 +212,57 @@ define float @fcvt_s_lu(i64 %a) nounwind {
}
define float @fcvt_s_w_i8(i8 signext %a) nounwind {
-; CHECKIF-LABEL: fcvt_s_w_i8:
-; CHECKIF: # %bb.0:
-; CHECKIF-NEXT: fcvt.s.w fa0, a0
-; CHECKIF-NEXT: ret
+; RV32IF-LABEL: fcvt_s_w_i8:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fcvt.s.w fa0, a0
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_w_i8:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.l fa0, a0
+; RV64IF-NEXT: ret
%1 = sitofp i8 %a to float
ret float %1
}
define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
-; CHECKIF-LABEL: fcvt_s_wu_i8:
-; CHECKIF: # %bb.0:
-; CHECKIF-NEXT: fcvt.s.wu fa0, a0
-; CHECKIF-NEXT: ret
+; RV32IF-LABEL: fcvt_s_wu_i8:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fcvt.s.wu fa0, a0
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_wu_i8:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.lu fa0, a0
+; RV64IF-NEXT: ret
%1 = uitofp i8 %a to float
ret float %1
}
define float @fcvt_s_w_i16(i16 signext %a) nounwind {
-; CHECKIF-LABEL: fcvt_s_w_i16:
-; CHECKIF: # %bb.0:
-; CHECKIF-NEXT: fcvt.s.w fa0, a0
-; CHECKIF-NEXT: ret
+; RV32IF-LABEL: fcvt_s_w_i16:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fcvt.s.w fa0, a0
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_w_i16:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.l fa0, a0
+; RV64IF-NEXT: ret
%1 = sitofp i16 %a to float
ret float %1
}
define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
-; CHECKIF-LABEL: fcvt_s_wu_i16:
-; CHECKIF: # %bb.0:
-; CHECKIF-NEXT: fcvt.s.wu fa0, a0
-; CHECKIF-NEXT: ret
+; RV32IF-LABEL: fcvt_s_wu_i16:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fcvt.s.wu fa0, a0
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_wu_i16:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.lu fa0, a0
+; RV64IF-NEXT: ret
%1 = uitofp i16 %a to float
ret float %1
}
@@ -245,7 +279,7 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
; RV64IF-LABEL: fcvt_s_w_demanded_bits:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1
-; RV64IF-NEXT: fcvt.s.w fa5, a0
+; RV64IF-NEXT: fcvt.s.l fa5, a0
; RV64IF-NEXT: fsw fa5, 0(a1)
; RV64IF-NEXT: ret
%3 = add i32 %0, 1
@@ -266,7 +300,9 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1
-; RV64IF-NEXT: fcvt.s.wu fa5, a0
+; RV64IF-NEXT: slli a2, a0, 32
+; RV64IF-NEXT: srli a2, a2, 32
+; RV64IF-NEXT: fcvt.s.lu fa5, a2
; RV64IF-NEXT: fsw fa5, 0(a1)
; RV64IF-NEXT: ret
%3 = add i32 %0, 1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
index 1afb1d9be6a099..b813a79c339ec5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
@@ -2,52 +2,6 @@
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
----
-name: sitofp_s64_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: sitofp_s64_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[FCVT_H_W:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_W [[COPY]], 7
- ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_W]]
- ; CHECK-NEXT: PseudoRET implicit $f10_h
- %0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:fprb(s16) = G_SITOFP %1(s32)
- $f10_h = COPY %2(s16)
- PseudoRET implicit $f10_h
-
-...
----
-name: uitofp_s64_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: uitofp_s64_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[FCVT_H_WU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_WU [[COPY]], 7
- ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_WU]]
- ; CHECK-NEXT: PseudoRET implicit $f10_h
- %0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:fprb(s16) = G_UITOFP %1(s32)
- $f10_h = COPY %2(s16)
- PseudoRET implicit $f10_h
-
-...
---
name: sitofp_s64_s64
legalized: true
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir
index 31175d7af93f98..f99a15a850517f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir
@@ -2,52 +2,6 @@
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
----
-name: sitofp_s32_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: sitofp_s32_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[FCVT_S_W:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_W [[COPY]], 7
- ; CHECK-NEXT: $f10_f = COPY [[FCVT_S_W]]
- ; CHECK-NEXT: PseudoRET implicit $f10_f
- %0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:fprb(s32) = G_SITOFP %1(s32)
- $f10_f = COPY %2(s32)
- PseudoRET implicit $f10_f
-
-...
----
-name: uitofp_s32_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: uitofp_s32_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[FCVT_S_WU:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_WU [[COPY]], 7
- ; CHECK-NEXT: $f10_f = COPY [[FCVT_S_WU]]
- ; CHECK-NEXT: PseudoRET implicit $f10_f
- %0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:fprb(s32) = G_UITOFP %1(s32)
- $f10_f = COPY %2(s32)
- PseudoRET implicit $f10_f
-
-...
---
name: sitofp_s32_s64
legalized: true
@@ -91,52 +45,6 @@ body: |
$f10_f = COPY %1(s32)
PseudoRET implicit $f10_f
-...
----
-name: sitofp_s64_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: sitofp_s64_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_W [[COPY]], 0
- ; CHECK-NEXT: $f10_d = COPY [[FCVT_D_W]]
- ; CHECK-NEXT: PseudoRET implicit $f10_d
- %0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:fprb(s64) = G_SITOFP %1(s32)
- $f10_d = COPY %2(s64)
- PseudoRET implicit $f10_d
-
-...
----
-name: uitofp_s64_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: uitofp_s64_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[FCVT_D_WU:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_WU [[COPY]], 0
- ; CHECK-NEXT: $f10_d = COPY [[FCVT_D_WU]]
- ; CHECK-NEXT: PseudoRET implicit $f10_d
- %0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:fprb(s64) = G_UITOFP %1(s32)
- $f10_d = COPY %2(s64)
- PseudoRET implicit $f10_d
-
...
---
name: sitofp_s64_s64
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
index 52c69d1acbffc7..6a70a331a02c8c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
@@ -13,11 +13,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s64)
; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
; CHECK-NEXT: PseudoRET implicit $f10_h
%1:_(s64) = COPY $x10
@@ -38,10 +37,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
; CHECK-NEXT: PseudoRET implicit $f10_h
%1:_(s64) = COPY $x10
@@ -62,11 +60,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s64)
; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
; CHECK-NEXT: PseudoRET implicit $f10_h
%1:_(s64) = COPY $x10
@@ -87,10 +84,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
; CHECK-NEXT: PseudoRET implicit $f10_h
%1:_(s64) = COPY $x10
@@ -111,11 +107,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s64)
; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
; CHECK-NEXT: PseudoRET implicit $f10_h
%1:_(s64) = COPY $x10
@@ -136,10 +131,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
; CHECK-NEXT: PseudoRET implicit $f10_h
%1:_(s64) = COPY $x10
@@ -160,8 +154,8 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[TRUNC]](s32)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[SEXT_INREG]](s64)
; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
; CHECK-NEXT: PseudoRET implicit $f10_h
%1:_(s64) = COPY $x10
@@ -182,8 +176,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[TRUNC]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
; CHECK-NEXT: PseudoRET implicit $f10_h
%1:_(s64) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir
index bc09a44dee2e09..2d6ee6250cf328 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir
@@ -13,11 +13,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s64)
; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%1:_(s64) = COPY $x10
@@ -38,10 +37,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%1:_(s64) = COPY $x10
@@ -62,11 +60,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s64)
; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%1:_(s64) = COPY $x10
@@ -87,10 +84,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%1:_(s64) = COPY $x10
@@ -111,11 +107,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s64)
; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%1:_(s64) = COPY $x10
@@ -136,10 +131,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%1:_(s64) = COPY $x10
@@ -160,8 +154,8 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[TRUNC]](s32)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s64)
; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%1:_(s64) = COPY $x10
@@ -182,8 +176,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[TRUNC]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%1:_(s64) = COPY $x10
@@ -244,11 +239,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s64)
; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%1:_(s64) = COPY $x10
@@ -269,10 +263,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%1:_(s64) = COPY $x10
@@ -293,11 +286,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s64)
; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%1:_(s64) = COPY $x10
@@ -318,10 +310,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%1:_(s64) = COPY $x10
@@ -342,11 +333,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s64)
; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%1:_(s64) = COPY $x10
@@ -367,10 +357,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%1:_(s64) = COPY $x10
@@ -391,8 +380,8 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[TRUNC]](s32)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s64)
; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%1:_(s64) = COPY $x10
@@ -413,8 +402,9 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[TRUNC]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s64)
; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%1:_(s64) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
index 10da1f8fc9fb30..5b48a7e947ae67 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
@@ -3,52 +3,6 @@
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
----
-name: sitofp_s16_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: sitofp_s16_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s16) = G_SITOFP [[TRUNC]](s32)
- ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16)
- ; CHECK-NEXT: PseudoRET implicit $f10_h
- %0:_(s64) = COPY $x10
- %1:_(s32) = G_TRUNC %0(s64)
- %2:_(s16) = G_SITOFP %1(s32)
- $f10_h = COPY %2(s16)
- PseudoRET implicit $f10_h
-
-...
----
-name: uitofp_s16_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: uitofp_s16_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s16) = G_UITOFP [[TRUNC]](s32)
- ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16)
- ; CHECK-NEXT: PseudoRET implicit $f10_h
- %0:_(s64) = COPY $x10
- %1:_(s32) = G_TRUNC %0(s64)
- %2:_(s16) = G_UITOFP %1(s32)
- $f10_h = COPY %2(s16)
- PseudoRET implicit $f10_h
-
-...
---
name: sitofp_s16_s64
legalized: true
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
index e0f039d5983ee8..6cb38cf38a6a56 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
@@ -3,52 +3,6 @@
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
----
-name: sitofp_s32_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: sitofp_s32_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[TRUNC]](s32)
- ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32)
- ; CHECK-NEXT: PseudoRET implicit $f10_f
- %0:_(s64) = COPY $x10
- %1:_(s32) = G_TRUNC %0(s64)
- %2:_(s32) = G_SITOFP %1(s32)
- $f10_f = COPY %2(s32)
- PseudoRET implicit $f10_f
-
-...
----
-name: uitofp_s32_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: uitofp_s32_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s32) = G_UITOFP [[TRUNC]](s32)
- ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32)
- ; CHECK-NEXT: PseudoRET implicit $f10_f
- %0:_(s64) = COPY $x10
- %1:_(s32) = G_TRUNC %0(s64)
- %2:_(s32) = G_UITOFP %1(s32)
- $f10_f = COPY %2(s32)
- PseudoRET implicit $f10_f
-
-...
---
name: sitofp_s32_s64
legalized: true
@@ -90,52 +44,6 @@ body: |
$f10_f = COPY %1(s32)
PseudoRET implicit $f10_f
-...
----
-name: sitofp_s64_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: sitofp_s64_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s64) = G_SITOFP [[TRUNC]](s32)
- ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64)
- ; CHECK-NEXT: PseudoRET implicit $f10_d
- %0:_(s64) = COPY $x10
- %1:_(s32) = G_TRUNC %0(s64)
- %2:_(s64) = G_SITOFP %1(s32)
- $f10_d = COPY %2(s64)
- PseudoRET implicit $f10_d
-
-...
----
-name: uitofp_s64_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10
-
- ; CHECK-LABEL: name: uitofp_s64_s32
- ; CHECK: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s64) = G_UITOFP [[TRUNC]](s32)
- ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64)
- ; CHECK-NEXT: PseudoRET implicit $f10_d
- %0:_(s64) = COPY $x10
- %1:_(s32) = G_TRUNC %0(s64)
- %2:_(s64) = G_UITOFP %1(s32)
- $f10_d = COPY %2(s64)
- PseudoRET implicit $f10_d
-
...
---
name: sitofp_s64_s64
>From 5899f5ea6d11424355ce721d0ca78a645e885f48 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 6 Nov 2024 20:30:48 -0800
Subject: [PATCH 2/2] fixup! Use computeNumSignBits.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 7 ++-
.../RISCV/GlobalISel/double-convert.ll | 44 ++++++-------------
.../CodeGen/RISCV/GlobalISel/float-convert.ll | 44 ++++++-------------
3 files changed, 33 insertions(+), 62 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 0161af27e496dd..d11647b78d7417 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -259,7 +259,8 @@ RISCVInstructionSelector::selectSExtBits(MachineOperand &Root,
unsigned Bits) const {
if (!Root.isReg())
return std::nullopt;
- MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
+ Register RootReg = Root.getReg();
+ MachineInstr *RootDef = MRI->getVRegDef(RootReg);
if (RootDef->getOpcode() == TargetOpcode::G_SEXT_INREG &&
RootDef->getOperand(2).getImm() == Bits) {
@@ -267,7 +268,9 @@ RISCVInstructionSelector::selectSExtBits(MachineOperand &Root,
{[=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); }}};
}
- // TODO: Use computeNumSignBits.
+ unsigned Size = MRI->getType(RootReg).getScalarSizeInBits();
+ if ((Size - KB->computeNumSignBits(RootReg)) < Bits)
+ return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
return std::nullopt;
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
index 231752c3842cd6..a2e812352df077 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
@@ -78,17 +78,11 @@ define double @fcvt_d_w(i32 %a) nounwind {
}
define double @fcvt_d_w_load(ptr %p) nounwind {
-; RV32IFD-LABEL: fcvt_d_w_load:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: lw a0, 0(a0)
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w_load:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lw a0, 0(a0)
-; RV64IFD-NEXT: fcvt.d.l fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w_load:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: lw a0, 0(a0)
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
%a = load i32, ptr %p
%1 = sitofp i32 %a to double
ret double %1
@@ -242,15 +236,10 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind {
}
define double @fcvt_d_w_i8(i8 signext %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_w_i8:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w_i8:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.l fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w_i8:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
%1 = sitofp i8 %a to double
ret double %1
}
@@ -265,15 +254,10 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
}
define double @fcvt_d_w_i16(i16 signext %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_w_i16:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w_i16:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.l fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w_i16:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
%1 = sitofp i16 %a to double
ret double %1
}
@@ -298,7 +282,7 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1
-; RV64IFD-NEXT: fcvt.d.l fa5, a0
+; RV64IFD-NEXT: fcvt.d.w fa5, a0
; RV64IFD-NEXT: fsd fa5, 0(a1)
; RV64IFD-NEXT: ret
%3 = add i32 %0, 1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
index c0a6e5a8b7f0b8..81735724056d3f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
@@ -81,17 +81,11 @@ define float @fcvt_s_w(i32 %a) nounwind {
}
define float @fcvt_s_w_load(ptr %p) nounwind {
-; RV32IF-LABEL: fcvt_s_w_load:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: lw a0, 0(a0)
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w_load:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: lw a0, 0(a0)
-; RV64IF-NEXT: fcvt.s.l fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w_load:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: lw a0, 0(a0)
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
%a = load i32, ptr %p
%1 = sitofp i32 %a to float
ret float %1
@@ -212,15 +206,10 @@ define float @fcvt_s_lu(i64 %a) nounwind {
}
define float @fcvt_s_w_i8(i8 signext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w_i8:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w_i8:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.l fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w_i8:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
%1 = sitofp i8 %a to float
ret float %1
}
@@ -235,15 +224,10 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
}
define float @fcvt_s_w_i16(i16 signext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w_i16:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w_i16:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.l fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w_i16:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
%1 = sitofp i16 %a to float
ret float %1
}
@@ -269,7 +253,7 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
; RV64IF-LABEL: fcvt_s_w_demanded_bits:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1
-; RV64IF-NEXT: fcvt.s.l fa5, a0
+; RV64IF-NEXT: fcvt.s.w fa5, a0
; RV64IF-NEXT: fsw fa5, 0(a1)
; RV64IF-NEXT: ret
%3 = add i32 %0, 1
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