[llvm] [RISCV][WIP] Let RA do the CSR saves. (PR #90819)

[Michael Maitland via llvm-commits]

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@@ -43,3 +43,23 @@ void RISCVMachineFunctionInfo::addSExt32Register(Register Reg) {
 bool RISCVMachineFunctionInfo::isSExt32Register(Register Reg) const {
   return is_contained(SExt32Registers, Reg);
 }
+
+void RISCVMachineFunctionInfo::recordCFIInfo(MachineInstr *MI, int Reg,
+                                             int FrameReg, int64_t Offset) {
+  assert(Reg >= 0 && "Negative dwarf reg number!");
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michaelmaitland wrote:

`assert FramReg > 0`?

https://github.com/llvm/llvm-project/pull/90819