[llvm] [RISCV] Add test cases for RV64 i128<->half/float/double (PR #115124)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Wed Nov 6 11:36:37 PST 2024

Previous message: [llvm] [RISCV] Add test cases for RV64 i128<->half/float/double (PR #115124)
Next message: [llvm] 4480a22 - [LV][EVL] Emit vp.merge intrinsic to enable out-loop reduction in EVL vectorization. (#101641)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/115124

Previous message: [llvm] [RISCV] Add test cases for RV64 i128<->half/float/double (PR #115124)
Next message: [llvm] 4480a22 - [LV][EVL] Emit vp.merge intrinsic to enable out-loop reduction in EVL vectorization. (#101641)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list