[llvm] [PowerPC] Fix vector_shuffle combines when inputs are scalar_to_vector of differing types. (PR #80784)
zhijian lin via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 6 10:15:54 PST 2024
================
@@ -15687,16 +15687,20 @@ static SDValue isScalarToVec(SDValue Op) {
// On little endian, that's just the corresponding element in the other
// half of the vector. On big endian, it is in the same half but right
// justified rather than left justified in that half.
-static void fixupShuffleMaskForPermutedSToV(SmallVectorImpl<int> &ShuffV,
- int LHSMaxIdx, int RHSMinIdx,
- int RHSMaxIdx, int HalfVec,
- unsigned ValidLaneWidth,
- const PPCSubtarget &Subtarget) {
- for (int i = 0, e = ShuffV.size(); i < e; i++) {
- int Idx = ShuffV[i];
- if ((Idx >= 0 && Idx < LHSMaxIdx) || (Idx >= RHSMinIdx && Idx < RHSMaxIdx))
- ShuffV[i] +=
- Subtarget.isLittleEndian() ? HalfVec : HalfVec - ValidLaneWidth;
+static void fixupShuffleMaskForPermutedSToV(
+ SmallVectorImpl<int> &ShuffV, int LHSFirstElt, int LHSLastElt,
+ int RHSFirstElt, int RHSLastElt, int HalfVec, unsigned LHSNumValidElts,
+ unsigned RHSNumValidElts, const PPCSubtarget &Subtarget) {
+ int LHSEltFixup =
+ Subtarget.isLittleEndian() ? HalfVec : HalfVec - LHSNumValidElts;
+ int RHSEltFixup =
+ Subtarget.isLittleEndian() ? HalfVec : HalfVec - RHSNumValidElts;
+ for (int I = 0, E = ShuffV.size(); I < E; ++I) {
+ int Idx = ShuffV[I];
+ if (Idx >= LHSFirstElt && Idx <= LHSLastElt)
+ ShuffV[I] += LHSEltFixup;
+ if (Idx >= RHSFirstElt && Idx <= RHSLastElt)
----------------
diggerlin wrote:
nit: change to
`else if (Idx >= RHSFirstElt && Idx <= RHSLastElt)`
https://github.com/llvm/llvm-project/pull/80784
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