[llvm] 83f92c3 - [RISCV] fix SP recovery in varargs functions (#114316)
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Wed Nov 6 08:30:37 PST 2024
Author: dlav-sc
Date: 2024-11-06T19:30:32+03:00
New Revision: 83f92c33a4b4bd703882e7e9bb2c5efd15042b96
URL: https://github.com/llvm/llvm-project/commit/83f92c33a4b4bd703882e7e9bb2c5efd15042b96
DIFF: https://github.com/llvm/llvm-project/commit/83f92c33a4b4bd703882e7e9bb2c5efd15042b96.diff
LOG: [RISCV] fix SP recovery in varargs functions (#114316)
This patch fixes sp recovery in the epilogue in varargs functions when
fp register is presented and second sp adjustment is applied.
Source of the issue: https://github.com/llvm/llvm-project/pull/110809
Added:
Modified:
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index e0abc2d812ccfc..30131862c11455 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -872,9 +872,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
uint64_t StackSize = FirstSPAdjustAmount ? FirstSPAdjustAmount
: getStackSizeWithRVVPadding(MF) -
RVFI->getReservedSpillsSize();
- uint64_t FPOffset = FirstSPAdjustAmount ? FirstSPAdjustAmount
- : getStackSizeWithRVVPadding(MF) -
- RVFI->getVarArgsSaveSize();
+ uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
uint64_t RVVStackSize = RVFI->getRVVStackSize();
bool RestoreSPFromFP = RI->hasStackRealignment(MF) ||
diff --git a/llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll b/llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
index 94c2a8d5a73316..73d3827b84758a 100644
--- a/llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
+++ b/llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
@@ -28,7 +28,7 @@ define dso_local void @_Z3fooPKcz(ptr noundef %0, ...) "frame-pointer"="all" {
; RV64V-NEXT: sd a0, -32(s0)
; RV64V-NEXT: addi a0, s0, 8
; RV64V-NEXT: sd a0, -40(s0)
-; RV64V-NEXT: addi sp, s0, -496
+; RV64V-NEXT: addi sp, s0, -432
; RV64V-NEXT: .cfi_def_cfa sp, 496
; RV64V-NEXT: ld ra, 424(sp) # 8-byte Folded Reload
; RV64V-NEXT: ld s0, 416(sp) # 8-byte Folded Reload
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