[llvm] 5a16ed9 - [RISCV] Add +unaligned-scalar-mem to spacemit-x60 (#115125)

[via llvm-commits]

Author: Luke Lau
Date: 2024-11-06T18:49:21+08:00
New Revision: 5a16ed96c5362aa8e9610fa266d6f6202b19edc3

URL: https://github.com/llvm/llvm-project/commit/5a16ed96c5362aa8e9610fa266d6f6202b19edc3
DIFF: https://github.com/llvm/llvm-project/commit/5a16ed96c5362aa8e9610fa266d6f6202b19edc3.diff

LOG: [RISCV] Add +unaligned-scalar-mem to spacemit-x60 (#115125)

I can't find any official documentation on this, but from other
discussions[^1] and my own testing the spacemit-x60 seems to support
unaligned scalar loads and stores.

They seem to be performant, and just from a quick test we get a 2.45%
speedup on 500.perlbench_r on the Banana Pi F3[^2].

This would allow it to take advantage of #107548.

[^1]:
https://github.com/llvm/llvm-project/issues/110454#issuecomment-2382199460
[^2]: https://lnt.lukelau.me/db_default/v4/nts/32

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVProcessors.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 5277752a38ad9e..e52a856183678a 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -476,7 +476,8 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
                                         FeatureStdExtZicond,
                                         FeatureStdExtZvfh,
                                         FeatureStdExtZvkt,
-                                        FeatureStdExtZvl256b]),
+                                        FeatureStdExtZvl256b,
+                                        FeatureUnalignedScalarMem]),
                                        [TuneDLenFactor2,
                                         TuneOptimizedNF2SegmentLoadStore,
                                         TuneOptimizedNF3SegmentLoadStore,