[llvm] 37ce189 - [RISCV] Add requirement of asserts

[Wang Pengcheng via llvm-commits]

Author: Wang Pengcheng
Date: 2024-11-06T17:01:24+08:00
New Revision: 37ce18951fded6be1de319b05b968918cb45c00b

URL: https://github.com/llvm/llvm-project/commit/37ce18951fded6be1de319b05b968918cb45c00b
DIFF: https://github.com/llvm/llvm-project/commit/37ce18951fded6be1de319b05b968918cb45c00b.diff

LOG: [RISCV] Add requirement of asserts

We forgot to add `REQUIRES: asserts` here.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/misched-mem-clustering.mir

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/misched-mem-clustering.mir b/llvm/test/CodeGen/RISCV/misched-mem-clustering.mir
index 006331f8e9f027..08df378f271897 100644
--- a/llvm/test/CodeGen/RISCV/misched-mem-clustering.mir
+++ b/llvm/test/CodeGen/RISCV/misched-mem-clustering.mir
@@ -12,6 +12,8 @@
 # RUN:     -start-before=machine-scheduler -stop-after=postmisched -o - 2>&1 < %s \
 # RUN:   | FileCheck -check-prefix=MEMCLUSTER %s
 
+# REQUIRES: asserts
+
 ...
 ---
 name:            mem_clustering_1