[llvm] 69d0bab - [RISCV] Add load/store clustering in post machine schedule (#111504)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 6 00:21:35 PST 2024
Author: BoyaoWang430
Date: 2024-11-06T16:21:30+08:00
New Revision: 69d0bab82689d470e3fd68f50ca8b8d28f3e2294
URL: https://github.com/llvm/llvm-project/commit/69d0bab82689d470e3fd68f50ca8b8d28f3e2294
DIFF: https://github.com/llvm/llvm-project/commit/69d0bab82689d470e3fd68f50ca8b8d28f3e2294.diff
LOG: [RISCV] Add load/store clustering in post machine schedule (#111504)
#73789 added load clustering and #73796 tried to add store clustering.
If post machine schedule is used, previous cluster of load/store which
formed in machine schedule may break. In order to solve this, add
load/sotre clustering to post machine schedule.
Added:
llvm/test/CodeGen/RISCV/misched-mem-clustering.mir
Modified:
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index daaf9d4075dc54..a5afbcfd79710f 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -99,6 +99,11 @@ static cl::opt<bool> EnableMISchedLoadStoreClustering(
cl::desc("Enable load and store clustering in the machine scheduler"),
cl::init(true));
+static cl::opt<bool> EnablePostMISchedLoadStoreClustering(
+ "riscv-postmisched-load-store-clustering", cl::Hidden,
+ cl::desc("Enable PostRA load and store clustering in the machine scheduler"),
+ cl::init(true));
+
static cl::opt<bool>
EnableVLOptimizer("riscv-enable-vl-optimizer",
cl::desc("Enable the RISC-V VL Optimizer pass"),
@@ -360,6 +365,19 @@ class RISCVPassConfig : public TargetPassConfig {
return DAG;
}
+ ScheduleDAGInstrs *
+ createPostMachineScheduler(MachineSchedContext *C) const override {
+ ScheduleDAGMI *DAG = nullptr;
+ if (EnablePostMISchedLoadStoreClustering) {
+ DAG = createGenericSchedPostRA(C);
+ DAG->addMutation(createLoadClusterDAGMutation(
+ DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
+ DAG->addMutation(createStoreClusterDAGMutation(
+ DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
+ }
+ return DAG;
+ }
+
void addIRPasses() override;
bool addPreISel() override;
void addCodeGenPrepare() override;
diff --git a/llvm/test/CodeGen/RISCV/misched-mem-clustering.mir b/llvm/test/CodeGen/RISCV/misched-mem-clustering.mir
new file mode 100644
index 00000000000000..006331f8e9f027
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/misched-mem-clustering.mir
@@ -0,0 +1,85 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -verify-misched -enable-post-misched=false \
+# RUN: -riscv-postmisched-load-store-clustering=false -debug-only=machine-scheduler \
+# RUN: -start-before=machine-scheduler -stop-after=postmisched -o - 2>&1 < %s \
+# RUN: | FileCheck -check-prefix=NOPOSTMISCHED %s
+# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -mattr=+use-postra-scheduler -verify-misched -enable-post-misched=true \
+# RUN: -riscv-postmisched-load-store-clustering=false -debug-only=machine-scheduler \
+# RUN: -start-before=machine-scheduler -stop-after=postmisched -o - 2>&1 < %s \
+# RUN: | FileCheck -check-prefix=NOCLUSTER %s
+# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -mattr=+use-postra-scheduler -verify-misched -enable-post-misched=true \
+# RUN: -debug-only=machine-scheduler \
+# RUN: -start-before=machine-scheduler -stop-after=postmisched -o - 2>&1 < %s \
+# RUN: | FileCheck -check-prefix=MEMCLUSTER %s
+
+...
+---
+name: mem_clustering_1
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x6, $x10, $x14, $x15, $x16, $x17
+ ; NOPOSTMISCHED-LABEL: name: mem_clustering_1
+ ; NOPOSTMISCHED: liveins: $x6, $x10, $x14, $x15, $x16, $x17
+ ; NOPOSTMISCHED-NEXT: {{ $}}
+ ; NOPOSTMISCHED-NEXT: renamable $x5 = LW renamable $x15, 0 :: (load (s32))
+ ; NOPOSTMISCHED-NEXT: renamable $x7 = LW renamable $x15, 8 :: (load (s32))
+ ; NOPOSTMISCHED-NEXT: renamable $x28 = LW renamable $x15, 16 :: (load (s32))
+ ; NOPOSTMISCHED-NEXT: renamable $x29 = LW renamable $x15, 24 :: (load (s32))
+ ; NOPOSTMISCHED-NEXT: renamable $x11 = ADDW renamable $x6, killed renamable $x5
+ ; NOPOSTMISCHED-NEXT: renamable $x13 = ADDW killed renamable $x7, killed renamable $x28
+ ; NOPOSTMISCHED-NEXT: renamable $x11 = ADDW killed renamable $x11, killed renamable $x13
+ ; NOPOSTMISCHED-NEXT: renamable $x6 = ADDW killed renamable $x11, killed renamable $x29
+ ; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 0 :: (store (s32))
+ ; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 8 :: (store (s32))
+ ; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 16 :: (store (s32))
+ ; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 24 :: (store (s32))
+ ; NOPOSTMISCHED-NEXT: PseudoRET
+ ;
+ ; NOCLUSTER-LABEL: name: mem_clustering_1
+ ; NOCLUSTER: liveins: $x6, $x10, $x14, $x15, $x16, $x17
+ ; NOCLUSTER-NEXT: {{ $}}
+ ; NOCLUSTER-NEXT: renamable $x5 = LW renamable $x15, 0 :: (load (s32))
+ ; NOCLUSTER-NEXT: SW renamable $x14, renamable $x15, 0 :: (store (s32))
+ ; NOCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x6, killed renamable $x5
+ ; NOCLUSTER-NEXT: renamable $x7 = LW renamable $x15, 8 :: (load (s32))
+ ; NOCLUSTER-NEXT: renamable $x28 = LW renamable $x15, 16 :: (load (s32))
+ ; NOCLUSTER-NEXT: renamable $x29 = LW renamable $x15, 24 :: (load (s32))
+ ; NOCLUSTER-NEXT: renamable $x13 = ADDW killed renamable $x7, killed renamable $x28
+ ; NOCLUSTER-NEXT: SW renamable $x14, renamable $x15, 8 :: (store (s32))
+ ; NOCLUSTER-NEXT: SW renamable $x14, renamable $x15, 16 :: (store (s32))
+ ; NOCLUSTER-NEXT: SW killed renamable $x14, killed renamable $x15, 24 :: (store (s32))
+ ; NOCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x11, killed renamable $x13
+ ; NOCLUSTER-NEXT: renamable $x6 = ADDW killed renamable $x11, killed renamable $x29
+ ; NOCLUSTER-NEXT: PseudoRET
+ ;
+ ; MEMCLUSTER-LABEL: name: mem_clustering_1
+ ; MEMCLUSTER: liveins: $x6, $x10, $x14, $x15, $x16, $x17
+ ; MEMCLUSTER-NEXT: {{ $}}
+ ; MEMCLUSTER-NEXT: renamable $x5 = LW renamable $x15, 0 :: (load (s32))
+ ; MEMCLUSTER-NEXT: renamable $x7 = LW renamable $x15, 8 :: (load (s32))
+ ; MEMCLUSTER-NEXT: renamable $x28 = LW renamable $x15, 16 :: (load (s32))
+ ; MEMCLUSTER-NEXT: renamable $x29 = LW renamable $x15, 24 :: (load (s32))
+ ; MEMCLUSTER-NEXT: SW renamable $x14, renamable $x15, 0 :: (store (s32))
+ ; MEMCLUSTER-NEXT: SW renamable $x14, renamable $x15, 8 :: (store (s32))
+ ; MEMCLUSTER-NEXT: SW renamable $x14, renamable $x15, 16 :: (store (s32))
+ ; MEMCLUSTER-NEXT: SW killed renamable $x14, killed renamable $x15, 24 :: (store (s32))
+ ; MEMCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x6, killed renamable $x5
+ ; MEMCLUSTER-NEXT: renamable $x13 = ADDW killed renamable $x7, killed renamable $x28
+ ; MEMCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x11, killed renamable $x13
+ ; MEMCLUSTER-NEXT: renamable $x6 = ADDW killed renamable $x11, killed renamable $x29
+ ; MEMCLUSTER-NEXT: PseudoRET
+ renamable $x5 = LW renamable $x15, 0 :: (load (s32))
+ renamable $x7 = LW renamable $x15, 8 :: (load (s32))
+ renamable $x28 = LW renamable $x15, 16 :: (load (s32))
+ renamable $x29 = LW renamable $x15, 24 :: (load (s32))
+ renamable $x11 = ADDW killed renamable $x6, killed renamable $x5
+ renamable $x13 = ADDW killed renamable $x7, killed renamable $x28
+ renamable $x11 = ADDW killed renamable $x11, killed renamable $x13
+ renamable $x6 = ADDW killed renamable $x11, killed renamable $x29
+ SW renamable $x14, renamable $x15, 0 :: (store (s32))
+ SW renamable $x14, renamable $x15, 8 :: (store (s32))
+ SW renamable $x14, renamable $x15, 16 :: (store (s32))
+ SW renamable $x14, renamable $x15, 24 :: (store (s32))
+ PseudoRET
+...
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