[llvm] f427004 - [RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 5 21:48:56 PST 2024
Author: Craig Topper
Date: 2024-11-05T21:48:38-08:00
New Revision: f4270045f49d4936cd1d60e49f780ae9b1c18fab
URL: https://github.com/llvm/llvm-project/commit/f4270045f49d4936cd1d60e49f780ae9b1c18fab
DIFF: https://github.com/llvm/llvm-project/commit/f4270045f49d4936cd1d60e49f780ae9b1c18fab.diff
LOG: [RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC
Added:
Modified:
llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll b/llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
index 80746863a41c76..8396d992164e40 100644
--- a/llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d \
; RUN: -disable-strictnode-mutation < %s | FileCheck %s -check-prefix=RV64ID
+; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64 \
+; RUN: -disable-strictnode-mutation < %s | FileCheck %s -check-prefix=RV64IDINX
; This file exhaustively checks double<->i32 conversions. In general,
; fcvt.l[u].d can be selected instead of fcvt.w[u].d because poison is
@@ -12,6 +14,11 @@ define i32 @aext_fptosi(double %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.w.d a0, fa0, rtz
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: aext_fptosi:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.w.d a0, a0, rtz
+; RV64IDINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -22,6 +29,11 @@ define signext i32 @sext_fptosi(double %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.w.d a0, fa0, rtz
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: sext_fptosi:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.w.d a0, a0, rtz
+; RV64IDINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -33,6 +45,13 @@ define zeroext i32 @zext_fptosi(double %a) nounwind strictfp {
; RV64ID-NEXT: slli a0, a0, 32
; RV64ID-NEXT: srli a0, a0, 32
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: zext_fptosi:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.w.d a0, a0, rtz
+; RV64IDINX-NEXT: slli a0, a0, 32
+; RV64IDINX-NEXT: srli a0, a0, 32
+; RV64IDINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -42,6 +61,11 @@ define i32 @aext_fptoui(double %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: aext_fptoui:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.wu.d a0, a0, rtz
+; RV64IDINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -52,6 +76,11 @@ define signext i32 @sext_fptoui(double %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: sext_fptoui:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.wu.d a0, a0, rtz
+; RV64IDINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -61,6 +90,11 @@ define zeroext i32 @zext_fptoui(double %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.lu.d a0, fa0, rtz
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: zext_fptoui:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.lu.d a0, a0, rtz
+; RV64IDINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -70,6 +104,11 @@ define double @uitofp_aext_i32_to_f64(i32 %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.d.wu fa0, a0
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: uitofp_aext_i32_to_f64:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.d.wu a0, a0
+; RV64IDINX-NEXT: ret
%1 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1
}
@@ -80,6 +119,11 @@ define double @uitofp_sext_i32_to_f64(i32 signext %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.d.wu fa0, a0
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: uitofp_sext_i32_to_f64:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.d.wu a0, a0
+; RV64IDINX-NEXT: ret
%1 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1
}
@@ -89,6 +133,11 @@ define double @uitofp_zext_i32_to_f64(i32 zeroext %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.d.wu fa0, a0
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: uitofp_zext_i32_to_f64:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.d.wu a0, a0
+; RV64IDINX-NEXT: ret
%1 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1
}
@@ -98,6 +147,11 @@ define double @sitofp_aext_i32_to_f64(i32 %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.d.w fa0, a0
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: sitofp_aext_i32_to_f64:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.d.w a0, a0
+; RV64IDINX-NEXT: ret
%1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1
}
@@ -108,6 +162,11 @@ define double @sitofp_sext_i32_to_f64(i32 signext %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.d.w fa0, a0
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: sitofp_sext_i32_to_f64:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.d.w a0, a0
+; RV64IDINX-NEXT: ret
%1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1
}
@@ -117,6 +176,11 @@ define double @sitofp_zext_i32_to_f64(i32 zeroext %a) nounwind strictfp {
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.d.w fa0, a0
; RV64ID-NEXT: ret
+;
+; RV64IDINX-LABEL: sitofp_zext_i32_to_f64:
+; RV64IDINX: # %bb.0:
+; RV64IDINX-NEXT: fcvt.d.w a0, a0
+; RV64IDINX-NEXT: ret
%1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret double %1
}
diff --git a/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll b/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
index b047e6b0d5b863..2b358ce075d608 100644
--- a/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck %s -check-prefix=RV64IF
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -target-abi=lp64 -verify-machineinstrs < %s \
+; RUN: -disable-strictnode-mutation | FileCheck %s -check-prefix=RV64IFINX
; This file exhaustively checks float<->i32 conversions. In general,
; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is
@@ -12,6 +14,11 @@ define i32 @aext_fptosi(float %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: aext_fptosi:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.w.s a0, a0, rtz
+; RV64IFINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -22,6 +29,11 @@ define signext i32 @sext_fptosi(float %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: sext_fptosi:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.w.s a0, a0, rtz
+; RV64IFINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -33,6 +45,13 @@ define zeroext i32 @zext_fptosi(float %a) nounwind strictfp {
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: zext_fptosi:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.w.s a0, a0, rtz
+; RV64IFINX-NEXT: slli a0, a0, 32
+; RV64IFINX-NEXT: srli a0, a0, 32
+; RV64IFINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -42,6 +61,11 @@ define i32 @aext_fptoui(float %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: aext_fptoui:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.wu.s a0, a0, rtz
+; RV64IFINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -52,6 +76,11 @@ define signext i32 @sext_fptoui(float %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: sext_fptoui:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.wu.s a0, a0, rtz
+; RV64IFINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -61,6 +90,11 @@ define zeroext i32 @zext_fptoui(float %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: zext_fptoui:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.lu.s a0, a0, rtz
+; RV64IFINX-NEXT: ret
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
ret i32 %1
}
@@ -70,6 +104,11 @@ define float @uitofp_aext_i32_to_f32(i32 %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: uitofp_aext_i32_to_f32:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.s.wu a0, a0
+; RV64IFINX-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
}
@@ -80,6 +119,11 @@ define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: uitofp_sext_i32_to_f32:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.s.wu a0, a0
+; RV64IFINX-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
}
@@ -89,6 +133,11 @@ define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: uitofp_zext_i32_to_f32:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.s.wu a0, a0
+; RV64IFINX-NEXT: ret
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
}
@@ -98,6 +147,11 @@ define float @sitofp_aext_i32_to_f32(i32 %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: sitofp_aext_i32_to_f32:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.s.w a0, a0
+; RV64IFINX-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
}
@@ -108,6 +162,11 @@ define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: sitofp_sext_i32_to_f32:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.s.w a0, a0
+; RV64IFINX-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
}
@@ -117,6 +176,11 @@ define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
+;
+; RV64IFINX-LABEL: sitofp_zext_i32_to_f32:
+; RV64IFINX: # %bb.0:
+; RV64IFINX-NEXT: fcvt.s.w a0, a0
+; RV64IFINX-NEXT: ret
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret float %1
}
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