[llvm] cbc7812 - [RISCV] Add Zdinx RUN line to rv64d-double-convert.ll. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-11-05T21:12:09-08:00
New Revision: cbc7812565b0b0d60c0dadbd3743650f863237d4

URL: https://github.com/llvm/llvm-project/commit/cbc7812565b0b0d60c0dadbd3743650f863237d4
DIFF: https://github.com/llvm/llvm-project/commit/cbc7812565b0b0d60c0dadbd3743650f863237d4.diff

LOG: [RISCV] Add Zdinx RUN line to rv64d-double-convert.ll. NFC

We already have a Zfinx RUN line for rv64f-float-convert.ll.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64d-double-convert.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll b/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
index ed764fd6f641ac..e6c6ea59ecc055 100644
--- a/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64d | FileCheck %s -check-prefix=RV64ID
+; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck %s -check-prefix=RV64IDINX
 
 ; This file exhaustively checks double<->i32 conversions. In general,
 ; fcvt.l[u].d can be selected instead of fcvt.w[u].d because poison is
@@ -12,6 +14,11 @@ define i32 @aext_fptosi(double %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.w.d a0, fa0, rtz
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: aext_fptosi:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.w.d a0, a0, rtz
+; RV64IDINX-NEXT:    ret
   %1 = fptosi double %a to i32
   ret i32 %1
 }
@@ -21,6 +28,11 @@ define signext i32 @sext_fptosi(double %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.w.d a0, fa0, rtz
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: sext_fptosi:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.w.d a0, a0, rtz
+; RV64IDINX-NEXT:    ret
   %1 = fptosi double %a to i32
   ret i32 %1
 }
@@ -32,6 +44,13 @@ define zeroext i32 @zext_fptosi(double %a) nounwind {
 ; RV64ID-NEXT:    slli a0, a0, 32
 ; RV64ID-NEXT:    srli a0, a0, 32
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: zext_fptosi:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.w.d a0, a0, rtz
+; RV64IDINX-NEXT:    slli a0, a0, 32
+; RV64IDINX-NEXT:    srli a0, a0, 32
+; RV64IDINX-NEXT:    ret
   %1 = fptosi double %a to i32
   ret i32 %1
 }
@@ -41,6 +60,11 @@ define i32 @aext_fptoui(double %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.wu.d a0, fa0, rtz
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: aext_fptoui:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.wu.d a0, a0, rtz
+; RV64IDINX-NEXT:    ret
   %1 = fptoui double %a to i32
   ret i32 %1
 }
@@ -50,6 +74,11 @@ define signext i32 @sext_fptoui(double %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.wu.d a0, fa0, rtz
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: sext_fptoui:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.wu.d a0, a0, rtz
+; RV64IDINX-NEXT:    ret
   %1 = fptoui double %a to i32
   ret i32 %1
 }
@@ -59,6 +88,11 @@ define zeroext i32 @zext_fptoui(double %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.lu.d a0, fa0, rtz
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: zext_fptoui:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.lu.d a0, a0, rtz
+; RV64IDINX-NEXT:    ret
   %1 = fptoui double %a to i32
   ret i32 %1
 }
@@ -68,6 +102,11 @@ define double @uitofp_aext_i32_to_f64(i32 %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.d.wu fa0, a0
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: uitofp_aext_i32_to_f64:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.d.wu a0, a0
+; RV64IDINX-NEXT:    ret
   %1 = uitofp i32 %a to double
   ret double %1
 }
@@ -77,6 +116,11 @@ define double @uitofp_sext_i32_to_f64(i32 signext %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.d.wu fa0, a0
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: uitofp_sext_i32_to_f64:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.d.wu a0, a0
+; RV64IDINX-NEXT:    ret
   %1 = uitofp i32 %a to double
   ret double %1
 }
@@ -86,6 +130,11 @@ define double @uitofp_zext_i32_to_f64(i32 zeroext %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.d.wu fa0, a0
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: uitofp_zext_i32_to_f64:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.d.wu a0, a0
+; RV64IDINX-NEXT:    ret
   %1 = uitofp i32 %a to double
   ret double %1
 }
@@ -95,6 +144,11 @@ define double @sitofp_aext_i32_to_f64(i32 %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.d.w fa0, a0
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: sitofp_aext_i32_to_f64:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.d.w a0, a0
+; RV64IDINX-NEXT:    ret
   %1 = sitofp i32 %a to double
   ret double %1
 }
@@ -104,6 +158,11 @@ define double @sitofp_sext_i32_to_f64(i32 signext %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.d.w fa0, a0
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: sitofp_sext_i32_to_f64:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.d.w a0, a0
+; RV64IDINX-NEXT:    ret
   %1 = sitofp i32 %a to double
   ret double %1
 }
@@ -113,6 +172,11 @@ define double @sitofp_zext_i32_to_f64(i32 zeroext %a) nounwind {
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.d.w fa0, a0
 ; RV64ID-NEXT:    ret
+;
+; RV64IDINX-LABEL: sitofp_zext_i32_to_f64:
+; RV64IDINX:       # %bb.0:
+; RV64IDINX-NEXT:    fcvt.d.w a0, a0
+; RV64IDINX-NEXT:    ret
   %1 = sitofp i32 %a to double
   ret double %1
 }