[llvm] [RISCV] Prefer strided load for interleave load with only one lane active (PR #115069)

[Luke Lau via llvm-commits]

lukel97 wrote:

> Note that I've seen the vectorizer emitting wide interleave loads to represent a strided load

I think long term we should teach the loop vectorizer it to emit strided loads when it has interleave groups with one member (in loop vectorizer parlance). That way we can properly cost model it too. 

@nikolaypanchenko was mentioning this a while ago, is there still plans to upstream this? https://github.com/llvm/llvm-project/pull/93972#issuecomment-2142655113

Mainly mentioning this because SLP can emit strided loads directly and it seems like that's the direction we should move in now that we have the VP strided load/store intrinsics

https://github.com/llvm/llvm-project/pull/115069