[llvm] [AMDGPU][True16][MC] VINTERP instructions supporting true16/fake16 (PR #113634)

[Joe Nash via llvm-commits]

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@@ -11,29 +11,30 @@
 //===----------------------------------------------------------------------===//
 
 class VINTERPe <VOPProfile P> : Enc64 {
-  bits<8> vdst;
+  bits<11> vdst;
   bits<4> src0_modifiers;
-  bits<9> src0;
+  bits<11> src0;
   bits<3> src1_modifiers;
-  bits<9> src1;
+  bits<11> src1;
   bits<3> src2_modifiers;
-  bits<9> src2;
+  bits<11> src2;
   bits<1> clamp;
   bits<3> waitexp;
 
   let Inst{31-26} = 0x33; // VOP3P encoding
   let Inst{25-24} = 0x1; // VINTERP sub-encoding
 
-  let Inst{7-0}   = vdst;
+  let Inst{7-0}   = vdst{7-0};
   let Inst{10-8}  = waitexp;
-  let Inst{11}    = !if(P.HasOpSel, src0_modifiers{2}, 0); // op_sel(0)
-  let Inst{12}    = !if(P.HasOpSel, src1_modifiers{2}, 0); // op_sel(1)
-  let Inst{13}    = !if(P.HasOpSel, src2_modifiers{2}, 0); // op_sel(2)
-  let Inst{14}    = !if(P.HasOpSel, src0_modifiers{3}, 0); // op_sel(3)
+  // 16-bit select fields which can be interpreted as OpSel or hi/lo suffix
----------------
Sisyph wrote:

OpSel and hi/lo suffix are equivalent, so the comment is a bit confusing. It could be as follows
```suggestion
  // Fields for hi/lo 16-bits of register selection
```

https://github.com/llvm/llvm-project/pull/113634