[llvm] [RISCV] fix SP recovery in varargs functions (PR #114316)

[via llvm-commits]

https://github.com/dlav-sc updated https://github.com/llvm/llvm-project/pull/114316

>From 39f58fb6660d76fb28a88e0b53fbc3ffc673dc8f Mon Sep 17 00:00:00 2001
From: Daniil Avdeev <daniil.avdeev at syntacore.com>
Date: Wed, 30 Oct 2024 21:07:49 +0000
Subject: [PATCH] [RISCV] fix SP recovery in varargs functions

---
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp              | 4 +---
 llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll | 2 +-
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index f5851f37154519..2ff78ce9ea9c65 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -809,9 +809,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
   uint64_t StackSize = FirstSPAdjustAmount ? FirstSPAdjustAmount
                                            : getStackSizeWithRVVPadding(MF) -
                                                  RVFI->getReservedSpillsSize();
-  uint64_t FPOffset = FirstSPAdjustAmount ? FirstSPAdjustAmount
-                                          : getStackSizeWithRVVPadding(MF) -
-                                                RVFI->getVarArgsSaveSize();
+  uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
   uint64_t RVVStackSize = RVFI->getRVVStackSize();
 
   bool RestoreFP = RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
diff --git a/llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll b/llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
index b350ceeee22d1b..0bc77cbef5b5a0 100644
--- a/llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
+++ b/llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
@@ -28,7 +28,7 @@ define dso_local void @_Z3fooPKcz(ptr noundef %0, ...) "frame-pointer"="all" {
 ; RV64V-NEXT:    sd a0, -32(s0)
 ; RV64V-NEXT:    addi a0, s0, 8
 ; RV64V-NEXT:    sd a0, -40(s0)
-; RV64V-NEXT:    addi sp, s0, -496
+; RV64V-NEXT:    addi sp, s0, -432
 ; RV64V-NEXT:    ld ra, 424(sp) # 8-byte Folded Reload
 ; RV64V-NEXT:    ld s0, 416(sp) # 8-byte Folded Reload
 ; RV64V-NEXT:    addi sp, sp, 496