[llvm] [AMDGPU] Improve isBasicBlockPrologue to only add necessary instructions (PR #113303)

[via llvm-commits]

alex-t wrote:

> > > > An instruction belongs to the prologue if it is part of the def-use chain that ends up on the exec mask writing instruction.
> > > 
> > > 
> > > Is this correct? like in the case below, the second sgpr-reload-from-vgpr is not in the prologue? v_readlane s0, v0, 1 `v_readlane s1, v0, 2` s_or_b32 exec, exec, s0
> > > >
> > 
> > 
> > Exactly. Only readlane producing s0 belongs to the prologue but another one, producing s1 does not.
> 
> If the second v_readlane is not the prologue, then `SkipPHIsAndLabels` would just return the insertion point between the two `v_readlane`s. This is not the right insertion point for vector instructions, right?
> 
I am unsure if the pattern you used as an example could exist.
If you look in the RegAllocFastImpl::getMBBBeginInsertionPoint you can see that all the reloads are inserted after the prologue except those producing operands for other prologue instructions.

`  

    // Most reloads should be inserted after prolog instructions.
    if (!TII->isBasicBlockPrologue(*I))
      break;

    // However if a prolog instruction reads a register that needs to be
    // reloaded, the reload should be inserted before the prolog.
    for (MachineOperand &MO : I->operands()) {
      if (MO.isReg())
        PrologLiveIns.insert(MO.getReg());
    }
`
So, I think that the "v_readlane s1, v0, 2" would be inserted after the "s_or_b32 exec, exec, s0"


https://github.com/llvm/llvm-project/pull/113303