[llvm] 3495d04 - [AMDGPU][MIR] Serialize SpillPhysVGPRs (#113129)

[via llvm-commits]

Author: Akshat Oke
Date: 2024-11-05T13:17:25+05:30
New Revision: 3495d0456021618be73de1ed0a3aa97952513ffc

URL: https://github.com/llvm/llvm-project/commit/3495d0456021618be73de1ed0a3aa97952513ffc
DIFF: https://github.com/llvm/llvm-project/commit/3495d0456021618be73de1ed0a3aa97952513ffc.diff

LOG: [AMDGPU][MIR] Serialize SpillPhysVGPRs (#113129)

Added: 
    llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
    llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
    llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 86d8dbe4d803cd..786baa6820e860 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1740,6 +1740,13 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
     MFI->setFlag(Info->VReg, Info->Flags);
   }
 
+  for (const auto &YamlRegStr : YamlMFI.SpillPhysVGPRS) {
+    Register ParsedReg;
+    if (parseRegister(YamlRegStr, ParsedReg))
+      return true;
+    MFI->SpillPhysVGPRs.push_back(ParsedReg);
+  }
+
   auto parseAndCheckArgument = [&](const std::optional<yaml::SIArgument> &A,
                                    const TargetRegisterClass &RC,
                                    ArgDescriptor &Arg, unsigned UserSGPRs,

diff  --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index e59dd724b94f8b..1e43d2727a00da 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -711,6 +711,9 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
       PSInputAddr(MFI.getPSInputAddr()),
       PSInputEnable(MFI.getPSInputEnable()),
       Mode(MFI.getMode()) {
+  for (Register Reg : MFI.getSGPRSpillPhysVGPRs())
+    SpillPhysVGPRS.push_back(regToString(Reg, TRI));
+
   for (Register Reg : MFI.getWWMReservedRegs())
     WWMReservedRegs.push_back(regToString(Reg, TRI));
 

diff  --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..018322eaa18665 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -275,6 +275,7 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
   // TODO: 10 may be a better default since it's the maximum.
   unsigned Occupancy = 0;
 
+  SmallVector<StringValue, 2> SpillPhysVGPRS;
   SmallVector<StringValue> WWMReservedRegs;
 
   StringValue ScratchRSrcReg = "$private_rsrc_reg";
@@ -336,6 +337,7 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
     YamlIO.mapOptional("highBitsOf32BitAddress",
                        MFI.HighBitsOf32BitAddress, 0u);
     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
+    YamlIO.mapOptional("spillPhysVGPRs", MFI.SpillPhysVGPRS);
     YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
     YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
     YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
@@ -610,6 +612,7 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction,
   }
 
   ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
+  ArrayRef<Register> getSGPRSpillPhysVGPRs() const { return SpillPhysVGPRs; }
 
   const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }
   const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
new file mode 100644
index 00000000000000..733b3522ac06e5
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
@@ -0,0 +1,12 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=ERR
+
+---
+name: invalid_reg_spill_phys_vgprs
+machineFunctionInfo:
+# ERR: [[@LINE+1]]:21: unknown register name 'notareg'
+  spillPhysVGPRs: ['$notareg']
+body: |
+  bb.0:
+    S_ENDPGM 0
+
+...

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
new file mode 100644
index 00000000000000..7275d3cce8766b
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
@@ -0,0 +1,12 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=ERR
+
+---
+name: invalid_reg_spill_phys_vgprs
+machineFunctionInfo:
+# ERR: [[@LINE+1]]:20: expected a named register
+  spillPhysVGPRs: [123]
+body: |
+  bb.0:
+    S_ENDPGM 0
+
+...

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
new file mode 100644
index 00000000000000..3961330070c779
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
@@ -0,0 +1,58 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa --start-before=si-lower-sgpr-spills --stop-after=prologepilog -o - %s | FileCheck %s
+
+# CHECK: csr_sgpr_spill
+# CHECK: spillPhysVGPRs
+# CHECK-NEXT: - '$vgpr0'
+---
+name: csr_sgpr_spill
+tracksRegLiveness: true
+body: |
+  bb.0:
+    S_NOP 0
+  bb.1:
+    $sgpr40 = S_MOV_B32 0
+    $sgpr41 = S_MOV_B32 1
+
+...
+
+# CHECK-LABEL: name: parse_none
+# CHECK: machineFunctionInfo:
+# CHECK-NOT: spillPhysVGPRs
+---
+name: parse_none
+machineFunctionInfo:
+  spillPhysVGPRs: []
+body: |
+  bb.0:
+    S_ENDPGM 0
+
+...
+
+# CHECK-LABEL: name: parse_one
+# CHECK: machineFunctionInfo:
+# CHECK: spillPhysVGPRs
+# CHECK-NEXT: - '$vgpr0'
+---
+name: parse_one
+machineFunctionInfo:
+  spillPhysVGPRs: ['$vgpr0']
+body: |
+  bb.0:
+    S_ENDPGM 0
+
+...
+
+# CHECK-LABEL: name: parse_two
+# CHECK: machineFunctionInfo:
+# CHECK: spillPhysVGPRs
+# CHECK-NEXT: - '$vgpr0'
+# CHECK-NEXT: - '$vgpr1'
+---
+name: parse_two
+machineFunctionInfo:
+  spillPhysVGPRs: ['$vgpr0', '$vgpr1']
+body: |
+  bb.0:
+    S_ENDPGM 0
+
+...