[llvm] [SelectionDAGBuilder][X86] Don't form FMAXNUM for f16 vectors if FMAXNUM needs to be promoted. (PR #114943)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/114943

In #70357, I changed a isLegalOrCustom to isLegalOrCustomOrPromote in visitSelect to enable integer min/max to be formed when the operation was promoted. Unfortunately, this also affected floating point. For floating point, fmaxnum may require a libcall so we also need to check if the operation on the promoted type is legal or custom.

Other changes to RISC-V have seen made the original change untested so this patch restores the original isLegalOrCustom.

Fixes #114520.

>From b7e50d28db88f7c94490a6541a921062e2c61b85 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 4 Nov 2024 21:31:58 -0800
Subject: [PATCH] [SelectionDAGBuilder][X86] Don't form FMAXNUM for f16 vectors
 if FMAXNUM needs to be promoted.

In #70357, I changed a isLegalOrCustom to isLegalOrCustomOrPromote
in visitSelect to enable integer min/max to be formed when the operation
was promoted. Unfortunately, this also affected floating point.
For floating point, fmaxnum may require a libcall so we also need
to check if the operation on the promoted type is legal or custom.

Other changes to RISC-V have seen made the original change untested
so this patch restores the original isLegalOrCustom.
---
 .../SelectionDAG/SelectionDAGBuilder.cpp      |  2 +-
 llvm/test/CodeGen/X86/pr114520.ll             | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/X86/pr114520.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 199d02afb97e3a..f8122b77b46def 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3775,7 +3775,7 @@ void SelectionDAGBuilder::visitSelect(const User &I) {
     }
 
     if (!IsUnaryAbs && Opc != ISD::DELETED_NODE &&
-        (TLI.isOperationLegalOrCustomOrPromote(Opc, VT) ||
+        (TLI.isOperationLegalOrCustom(Opc, VT) ||
          (UseScalarMinMax &&
           TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
         // If the underlying comparison instruction is used by any other
diff --git a/llvm/test/CodeGen/X86/pr114520.ll b/llvm/test/CodeGen/X86/pr114520.ll
new file mode 100644
index 00000000000000..f9dd3fce8c1ec0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr114520.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-none-unknown-elf -mattr=+avx512vl | FileCheck %s
+
+define half @r_2_10001(half %0) {
+; CHECK-LABEL: r_2_10001:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpextrw $0, %xmm0, %eax
+; CHECK-NEXT:    vmovd %eax, %xmm0
+; CHECK-NEXT:    vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT:    vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT:    movl $64512, %ecx # imm = 0xFC00
+; CHECK-NEXT:    cmoval %eax, %ecx
+; CHECK-NEXT:    vpinsrw $0, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+entry:
+  %cmp2 = fcmp ogt half %0, 0xHFC00
+  %cond.v = select i1 %cmp2, half %0, half 0xHFC00
+  ret half %cond.v
+}