[llvm] [AMDGPU][MIR] Serialize SpillPhysVGPRs (PR #113129)
Akshat Oke via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 4 22:53:10 PST 2024
https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/113129
>From cc814895ffa1c2ee4f86eca3c5bce8c364a96c89 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Mon, 21 Oct 2024 06:12:41 +0000
Subject: [PATCH 1/4] [AMDGPU][MIR] Serialize SpillPhysVGPRs
---
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 +++
.../Target/AMDGPU/SIMachineFunctionInfo.cpp | 3 +
.../lib/Target/AMDGPU/SIMachineFunctionInfo.h | 3 +
.../CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir | 57 +++++++++++++++++++
4 files changed, 70 insertions(+)
create mode 100644 llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 86d8dbe4d803cd..786baa6820e860 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1740,6 +1740,13 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->setFlag(Info->VReg, Info->Flags);
}
+ for (const auto &YamlRegStr : YamlMFI.SpillPhysVGPRS) {
+ Register ParsedReg;
+ if (parseRegister(YamlRegStr, ParsedReg))
+ return true;
+ MFI->SpillPhysVGPRs.push_back(ParsedReg);
+ }
+
auto parseAndCheckArgument = [&](const std::optional<yaml::SIArgument> &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index e59dd724b94f8b..1e43d2727a00da 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -711,6 +711,9 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
PSInputAddr(MFI.getPSInputAddr()),
PSInputEnable(MFI.getPSInputEnable()),
Mode(MFI.getMode()) {
+ for (Register Reg : MFI.getSGPRSpillPhysVGPRs())
+ SpillPhysVGPRS.push_back(regToString(Reg, TRI));
+
for (Register Reg : MFI.getWWMReservedRegs())
WWMReservedRegs.push_back(regToString(Reg, TRI));
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..018322eaa18665 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -275,6 +275,7 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
// TODO: 10 may be a better default since it's the maximum.
unsigned Occupancy = 0;
+ SmallVector<StringValue, 2> SpillPhysVGPRS;
SmallVector<StringValue> WWMReservedRegs;
StringValue ScratchRSrcReg = "$private_rsrc_reg";
@@ -336,6 +337,7 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
YamlIO.mapOptional("highBitsOf32BitAddress",
MFI.HighBitsOf32BitAddress, 0u);
YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
+ YamlIO.mapOptional("spillPhysVGPRs", MFI.SpillPhysVGPRS);
YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
@@ -610,6 +612,7 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction,
}
ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
+ ArrayRef<Register> getSGPRSpillPhysVGPRs() const { return SpillPhysVGPRs; }
const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }
const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
new file mode 100644
index 00000000000000..083ebcd9fa5683
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
@@ -0,0 +1,57 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa --start-before=si-lower-sgpr-spills --stop-after=prologepilog -o - %s | FileCheck %s
+
+# CHECK: csr_sgpr_spill
+# CHECK: spillPhysVGPRs:
+# CHECK-NEXT: - '$vgpr0'
+---
+name: csr_sgpr_spill
+tracksRegLiveness: true
+body: |
+ bb.0:
+ S_NOP 0
+ bb.1:
+ $sgpr40 = S_MOV_B32 0
+ $sgpr41 = S_MOV_B32 1
+
+...
+
+# CHECK-LABEL: name: parse_none
+# CHECK: machineFunctionInfo:
+# CHECK-NOT: spillPhysVGPRs:
+---
+name: parse_none
+machineFunctionInfo:
+ spillPhysVGPRs: []
+body: |
+ bb.0:
+ S_ENDPGM 0
+
+...
+
+# CHECK-LABEL: name: parse_one
+# CHECK: machineFunctionInfo:
+# CHECK: spillPhysVGPRs:
+# CHECK-NEXT: - '$vgpr0'
+---
+name: parse_one
+machineFunctionInfo:
+ spillPhysVGPRs: ['$vgpr0']
+body: |
+ bb.0:
+ S_ENDPGM 0
+
+...
+
+# CHECK-LABEL: name: parse_one
+# CHECK: machineFunctionInfo:
+# CHECK: spillPhysVGPRs:
+# CHECK-NEXT: - '$vgpr0'
+---
+name: parse_one
+machineFunctionInfo:
+ spillPhysVGPRs: ['$vgpr0']
+body: |
+ bb.0:
+ S_ENDPGM 0
+
+...
>From 86b0016448eedff5eae59a6f428be8d0788f3b91 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Tue, 22 Oct 2024 09:21:54 +0000
Subject: [PATCH 2/4] AS
---
llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
index 083ebcd9fa5683..3961330070c779 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
@@ -1,7 +1,7 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa --start-before=si-lower-sgpr-spills --stop-after=prologepilog -o - %s | FileCheck %s
# CHECK: csr_sgpr_spill
-# CHECK: spillPhysVGPRs:
+# CHECK: spillPhysVGPRs
# CHECK-NEXT: - '$vgpr0'
---
name: csr_sgpr_spill
@@ -17,7 +17,7 @@ body: |
# CHECK-LABEL: name: parse_none
# CHECK: machineFunctionInfo:
-# CHECK-NOT: spillPhysVGPRs:
+# CHECK-NOT: spillPhysVGPRs
---
name: parse_none
machineFunctionInfo:
@@ -30,7 +30,7 @@ body: |
# CHECK-LABEL: name: parse_one
# CHECK: machineFunctionInfo:
-# CHECK: spillPhysVGPRs:
+# CHECK: spillPhysVGPRs
# CHECK-NEXT: - '$vgpr0'
---
name: parse_one
@@ -42,14 +42,15 @@ body: |
...
-# CHECK-LABEL: name: parse_one
+# CHECK-LABEL: name: parse_two
# CHECK: machineFunctionInfo:
-# CHECK: spillPhysVGPRs:
+# CHECK: spillPhysVGPRs
# CHECK-NEXT: - '$vgpr0'
+# CHECK-NEXT: - '$vgpr1'
---
-name: parse_one
+name: parse_two
machineFunctionInfo:
- spillPhysVGPRs: ['$vgpr0']
+ spillPhysVGPRs: ['$vgpr0', '$vgpr1']
body: |
bb.0:
S_ENDPGM 0
>From 616f534fe77b22600c9127d34d3a9277e1f8fae8 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Tue, 22 Oct 2024 09:22:07 +0000
Subject: [PATCH 3/4] Add reg parse failure test
---
.../CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir | 12 ++++++++++++
1 file changed, 12 insertions(+)
create mode 100644 llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
new file mode 100644
index 00000000000000..733b3522ac06e5
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
@@ -0,0 +1,12 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=ERR
+
+---
+name: invalid_reg_spill_phys_vgprs
+machineFunctionInfo:
+# ERR: [[@LINE+1]]:21: unknown register name 'notareg'
+ spillPhysVGPRs: ['$notareg']
+body: |
+ bb.0:
+ S_ENDPGM 0
+
+...
>From aa768323707ee2ac8fa92c05c6ad69db43033e66 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Tue, 5 Nov 2024 06:48:05 +0000
Subject: [PATCH 4/4] add not a reg test
---
.../MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir | 12 ++++++++++++
1 file changed, 12 insertions(+)
create mode 100644 llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
new file mode 100644
index 00000000000000..7275d3cce8766b
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
@@ -0,0 +1,12 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=ERR
+
+---
+name: invalid_reg_spill_phys_vgprs
+machineFunctionInfo:
+# ERR: [[@LINE+1]]:20: expected a named register
+ spillPhysVGPRs: [123]
+body: |
+ bb.0:
+ S_ENDPGM 0
+
+...
More information about the llvm-commits
mailing list