[llvm] [RISCV] Lower fixed-length strided VP loads and stores for zvfhmin/zvfbfmin (PR #114750)

[Craig Topper via llvm-commits]

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@@ -1347,6 +1347,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
         setOperationAction({ISD::STRICT_FP_ROUND, ISD::STRICT_FP_EXTEND}, VT,
                            Custom);
 
+        setOperationAction({ISD::EXPERIMENTAL_VP_STRIDED_LOAD,
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topperc wrote:

There's a FIXME on line 1342 that should be changed.

https://github.com/llvm/llvm-project/pull/114750