[llvm] 176d653 - [RISCV] Add tests for single source interleave shuffles

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2024-11-04T13:08:05-08:00
New Revision: 176d6535ae417364622ef547099bef3c525b1f0f

URL: https://github.com/llvm/llvm-project/commit/176d6535ae417364622ef547099bef3c525b1f0f
DIFF: https://github.com/llvm/llvm-project/commit/176d6535ae417364622ef547099bef3c525b1f0f.diff

LOG: [RISCV] Add tests for single source interleave shuffles

These are failing to match vnsrl because we only check for the dual source
form.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
index f94494bbedde92..3af3540e1964b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
@@ -438,3 +438,37 @@ entry:
   store <8 x i8> %shuffle.i5, ptr %out, align 1
   ret void
 }
+
+define void @vnsrl_0_i8_single_src(ptr %in, ptr %out) {
+; CHECK-LABEL: vnsrl_0_i8_single_src:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vid.v v9
+; CHECK-NEXT:    vadd.vv v9, v9, v9
+; CHECK-NEXT:    vrgather.vv v10, v8, v9
+; CHECK-NEXT:    vse8.v v10, (a1)
+; CHECK-NEXT:    ret
+entry:
+  %0 = load <8 x i8>, ptr %in, align 1
+  %shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+  store <8 x i8> %shuffle.i5, ptr %out, align 1
+  ret void
+}
+
+define void @vnsrl_0_i8_single_src2(ptr %in, ptr %out) {
+; CHECK-LABEL: vnsrl_0_i8_single_src2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vid.v v9
+; CHECK-NEXT:    vadd.vv v9, v9, v9
+; CHECK-NEXT:    vrgather.vv v10, v8, v9
+; CHECK-NEXT:    vse8.v v10, (a1)
+; CHECK-NEXT:    ret
+entry:
+  %0 = load <8 x i8>, ptr %in, align 1
+  %shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>
+  store <8 x i8> %shuffle.i5, ptr %out, align 1
+  ret void
+}