[llvm] [TableGen] Make `!and` and `!or` short-circuit (PR #113963)

[Min-Yih Hsu via llvm-commits]

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@@ -67,6 +67,24 @@ def rec7 {
   bits<3> flags = { true, false, true };
 }
 
+// `!and` and `!or` should be short-circuit such that `!tail` on empty list will never
+// be evaluated.
+// CHECK: def rec8
+// CHECK:   list<int> newSeq = [];
+// CHECK:   list<int> newSeq2 = [];
+// CHECK:   list<int> newSeq3 = [];
+// CHECK:   list<int> newSeq4 = [];
+
+class Foo <list<int> seq = []> {
+  bit containsStr = !ne(!find(NAME, "BAR"), -1);
+  list<int> newSeq  = !if(!and(!not(!empty(seq)), containsStr), !tail(seq), seq);
+  list<int> newSeq2 = !if(!and(containsStr, !not(!empty(seq))), !tail(seq), seq);
+  list<int> newSeq3 = !if(!or(containsStr, -1), seq, !tail(seq));
+  list<int> newSeq4 = !if(!or(-1, containsStr), seq, !tail(seq));
+}
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mshockwave wrote:

Done

https://github.com/llvm/llvm-project/pull/113963