[llvm] a15bf88 - [SLP][NFC]Add a test with missing freeze instruction before reduction, NFC

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2024-11-04T04:38:09-08:00
New Revision: a15bf88d532ad2e81d7c54c480707f6c7d8bbeab

URL: https://github.com/llvm/llvm-project/commit/a15bf88d532ad2e81d7c54c480707f6c7d8bbeab
DIFF: https://github.com/llvm/llvm-project/commit/a15bf88d532ad2e81d7c54c480707f6c7d8bbeab.diff

LOG: [SLP][NFC]Add a test with missing freeze instruction before reduction, NFC

Added: 
    llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll b/llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll
new file mode 100644
index 00000000000000..ac47c60d7577b4
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer < %s | FileCheck %s
+
+define i1 @test(i32 %x, i32 %a, i32 %b, i32 %c, i32 %d) {
+; CHECK-LABEL: define i1 @test(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[D]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[B]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[C]], i32 2
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[X]], i32 3
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp sgt <4 x i32> [[TMP4]], <i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP5]])
+; CHECK-NEXT:    ret i1 [[TMP6]]
+;
+  %cmp = icmp sgt i32 %x, 1
+  %cmp2 = icmp sgt i32 %b, 1
+  %cmp3 = icmp sgt i32 %c, 1
+  %cmp4 = icmp sgt i32 %d, 1
+  %sel2 = select i1 %cmp4, i1 true, i1 %cmp2
+  %sel3 = select i1 %sel2, i1 true, i1 %cmp3
+  %sel4 = select i1 %cmp, i1 true, i1 %cmp4
+  %ret = or i1 %sel3, %sel4
+  ret i1 %ret
+}