[llvm] [X86][AMX] Reserve all pair registers when AMXTRANSPOSE is not ready (PR #114706)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

Author: Phoebe Wang (phoebewang)

<details>
<summary>Changes</summary>

Another try to fix compile regression by #<!-- -->113532

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Full diff: https://github.com/llvm/llvm-project/pull/114706.diff


1 Files Affected:

- (modified) llvm/lib/Target/X86/X86RegisterInfo.cpp (+5) 


``````````diff
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 2daaa95b06be0d..d025625ec8890d 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -645,6 +645,11 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   // Reserve low half pair registers in case they are used by RA aggressively.
   Reserved.set(X86::TMM0_TMM1);
   Reserved.set(X86::TMM2_TMM3);
+  // Reserve other pair registers.
+  if (!MF.getSubtarget<X86Subtarget>().hasAMXTRANSPOSE()) {
+    Reserved.set(X86::TMM4_TMM5);
+    Reserved.set(X86::TMM6_TMM7);
+  }
 
   assert(checkAllSuperRegsMarked(Reserved,
                                  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,

``````````

</details>


https://github.com/llvm/llvm-project/pull/114706