[llvm] [X86][AMX] Reserve all pair registers when AMXTRANSPOSE is not ready (PR #114706)

[Phoebe Wang via llvm-commits]

https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/114706

Another try to fix compile regression by #113532

>From fc714a92365efbb54a7242095638c6841f7a63e0 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe" <phoebe.wang at intel.com>
Date: Sun, 3 Nov 2024 21:22:25 +0800
Subject: [PATCH] [X86][AMX] Reserve all pair registers when AMXTRANSPOSE is
 not ready

Another try to fix compile regression by #113532
---
 llvm/lib/Target/X86/X86RegisterInfo.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 2daaa95b06be0d..d025625ec8890d 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -645,6 +645,11 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   // Reserve low half pair registers in case they are used by RA aggressively.
   Reserved.set(X86::TMM0_TMM1);
   Reserved.set(X86::TMM2_TMM3);
+  // Reserve other pair registers.
+  if (!MF.getSubtarget<X86Subtarget>().hasAMXTRANSPOSE()) {
+    Reserved.set(X86::TMM4_TMM5);
+    Reserved.set(X86::TMM6_TMM7);
+  }
 
   assert(checkAllSuperRegsMarked(Reserved,
                                  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,