[llvm] [X86][AMX] Move TPAIRS into PositionOrder 3, NFCI (PR #114642)

[Phoebe Wang via llvm-commits]

https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/114642

Should solve compile time regression.

>From cfffd5acdb5d927493bd0318bb08f91e3ee02422 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe" <phoebe.wang at intel.com>
Date: Sat, 2 Nov 2024 12:56:32 +0800
Subject: [PATCH] [X86][AMX] Move TPAIRS into PositionOrder 3, NFCI

Should solve compile time regression.
---
 llvm/lib/Target/X86/X86RegisterInfo.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 19a0b37d06a2a5..f93f920b6aeca3 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -432,11 +432,11 @@ def TMM4:  X86Reg<"tmm4",   4>;
 def TMM5:  X86Reg<"tmm5",   5>;
 def TMM6:  X86Reg<"tmm6",   6>;
 def TMM7:  X86Reg<"tmm7",   7>;
-}
 // TMM register pairs
 def TPAIRS : RegisterTuples<[sub_t0, sub_t1],
                             [(add TMM0, TMM2, TMM4, TMM6),
                              (add TMM1, TMM3, TMM5, TMM7)]>;
+}
 
 // Floating point stack registers. These don't map one-to-one to the FP
 // pseudo registers, but we still mark them as aliasing FP registers. That