[llvm] [AArch64] Lower EXT to ISD::VECTOR_SPLICE iso AArch64ISD::EXT (PR #114411)

[Paul Walker via llvm-commits]

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@@ -21443,10 +21443,11 @@ static SDValue LowerSVEIntrinsicEXT(SDNode *N, SelectionDAG &DAG) {
   // Convert everything to the domain of EXT (i.e bytes).
   SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, ByteVT, N->getOperand(1));
   SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, ByteVT, N->getOperand(2));
-  SDValue Op2 = DAG.getNode(ISD::MUL, dl, MVT::i32, N->getOperand(3),
-                            DAG.getConstant(ElemSize, dl, MVT::i32));
+  SDValue Op2 = DAG.getNode(ISD::MUL, dl, MVT::i64,
+                            DAG.getZExtOrTrunc(N->getOperand(3), dl, MVT::i64),
+                            DAG.getConstant(ElemSize, dl, MVT::i64));
 
-  SDValue EXT = DAG.getNode(AArch64ISD::EXT, dl, ByteVT, Op0, Op1, Op2);
+  SDValue EXT = DAG.getNode(ISD::VECTOR_SPLICE, dl, ByteVT, Op0, Op1, Op2);
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paulwalker-arm wrote:

This is not valid because `AArch64ISD::EXT` has a defined result when the index is out of range (it returns the first operand) but `ISD::VECTOR_SPLICE` specifically states its result is undefined.

https://github.com/llvm/llvm-project/pull/114411