[llvm] [AArch64] Lower EXT to ISD::VECTOR_SPLICE iso AArch64ISD::EXT (PR #114411)
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Thu Oct 31 07:52:31 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Sander de Smalen (sdesmalen-arm)
<details>
<summary>Changes</summary>
This is intended to be NFC, although it improves a test (because the unnecessary ext is now folded away).
---
Full diff: https://github.com/llvm/llvm-project/pull/114411.diff
5 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+4-3)
- (modified) llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (+1-18)
- (modified) llvm/lib/Target/AArch64/SVEInstrFormats.td (+15-2)
- (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll (-1)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 2120443b6ba2c5..cadfbc93857080 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -310,7 +310,7 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
if (MulImm >= 0 && MulImm <= Max) {
MulImm *= Scale;
- Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32);
+ Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i64);
return true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e8c02c09879747..2671660958767c 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -21443,10 +21443,11 @@ static SDValue LowerSVEIntrinsicEXT(SDNode *N, SelectionDAG &DAG) {
// Convert everything to the domain of EXT (i.e bytes).
SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, ByteVT, N->getOperand(1));
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, ByteVT, N->getOperand(2));
- SDValue Op2 = DAG.getNode(ISD::MUL, dl, MVT::i32, N->getOperand(3),
- DAG.getConstant(ElemSize, dl, MVT::i32));
+ SDValue Op2 = DAG.getNode(ISD::MUL, dl, MVT::i64,
+ DAG.getZExtOrTrunc(N->getOperand(3), dl, MVT::i64),
+ DAG.getConstant(ElemSize, dl, MVT::i64));
- SDValue EXT = DAG.getNode(AArch64ISD::EXT, dl, ByteVT, Op0, Op1, Op2);
+ SDValue EXT = DAG.getNode(ISD::VECTOR_SPLICE, dl, ByteVT, Op0, Op1, Op2);
return DAG.getNode(ISD::BITCAST, dl, VT, EXT);
}
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 6fdcaec86340ce..62c70122a8024e 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -936,7 +936,7 @@ let Predicates = [HasNonStreamingSVEorSME2p2] in {
let Predicates = [HasSVEorSME] in {
defm INSR_ZR : sve_int_perm_insrs<"insr", AArch64insr>;
defm INSR_ZV : sve_int_perm_insrv<"insr", AArch64insr>;
- defm EXT_ZZI : sve_int_perm_extract_i<"ext", AArch64ext>;
+ defm EXT_ZZI : sve_int_perm_extract_i<"ext", vector_splice>;
defm RBIT_ZPmZ : sve_int_perm_rev_rbit<"rbit", AArch64rbit_mt>;
defm REVB_ZPmZ : sve_int_perm_rev_revb<"revb", AArch64revb_mt>;
@@ -2045,23 +2045,6 @@ let Predicates = [HasSVEorSME] in {
(INSR_ZV_D ZPR:$Z2, (INSERT_SUBREG (IMPLICIT_DEF),
(LASTB_VPZ_D (PTRUE_D 31), ZPR:$Z1), dsub))>;
- // Splice with lane bigger or equal to 0
- foreach VT = [nxv16i8] in
- def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_255 i32:$index)))),
- (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>;
-
- foreach VT = [nxv8i16, nxv8f16, nxv8bf16] in
- def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_127 i32:$index)))),
- (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>;
-
- foreach VT = [nxv4i32, nxv4f16, nxv4f32, nxv4bf16] in
- def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_63 i32:$index)))),
- (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>;
-
- foreach VT = [nxv2i64, nxv2f16, nxv2f32, nxv2f64, nxv2bf16] in
- def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_31 i32:$index)))),
- (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>;
-
defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs", SETUGE, SETULE>;
defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi", SETUGT, SETULT>;
defm CMPGE_PPzZZ : sve_int_cmp_0<0b100, "cmpge", SETGE, SETLE>;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 5cfcc01afd20f3..caa4d7dbc172c5 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -1784,8 +1784,21 @@ class sve_int_perm_extract_i<string asm>
multiclass sve_int_perm_extract_i<string asm, SDPatternOperator op> {
def NAME : sve_int_perm_extract_i<asm>;
- def : SVE_3_Op_Imm_Pat<nxv16i8, op, nxv16i8, nxv16i8, i32, imm0_255,
- !cast<Instruction>(NAME)>;
+ foreach VT = [nxv16i8] in
+ def : Pat<(VT (op VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_255 i32:$index)))),
+ (!cast<Instruction>(NAME) ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>;
+
+ foreach VT = [nxv8i16, nxv8f16, nxv8bf16] in
+ def : Pat<(VT (op VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_127 i32:$index)))),
+ (!cast<Instruction>(NAME) ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>;
+
+ foreach VT = [nxv4i32, nxv4f16, nxv4f32, nxv4bf16] in
+ def : Pat<(VT (op VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_63 i32:$index)))),
+ (!cast<Instruction>(NAME) ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>;
+
+ foreach VT = [nxv2i64, nxv2f16, nxv2f32, nxv2f64, nxv2bf16] in
+ def : Pat<(VT (op VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_31 i32:$index)))),
+ (!cast<Instruction>(NAME) ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>;
}
class sve2_int_perm_extract_i_cons<string asm>
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
index fec255b712441e..ba99185a452510 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
@@ -641,7 +641,6 @@ define <vscale x 16 x i8> @ext_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
define <vscale x 8 x i16> @ext_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: ext_i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext z0.b, z0.b, z1.b, #0
; CHECK-NEXT: ret
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %a,
<vscale x 8 x i16> %b,
``````````
</details>
https://github.com/llvm/llvm-project/pull/114411
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