[llvm] [DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (PR #114389)
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llvm-commits at lists.llvm.org
Thu Oct 31 07:38:09 PDT 2024
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@@ -808,6 +808,23 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
}
break;
}
+ case ISD::SRL: {
+ // If we are only demanding sign bits then we can use the shift source
+ // directly.
+ if (std::optional<uint64_t> MaxSA =
+ DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1)) {
+ SDValue Op0 = Op.getOperand(0);
+ unsigned ShAmt = *MaxSA;
+ unsigned NumSignBits =
+ DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
+ // Must already be signbits in DemandedBits bounds, and can't demand any
+ // shifted in zeroes.
+ if (DemandedBits.countl_zero() >= ShAmt &&
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goldsteinn wrote:
nit: guard the `ComputeNumSignBits` behind this check.
https://github.com/llvm/llvm-project/pull/114389
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