[llvm] [DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (PR #114389)

[Simon Pilgrim via llvm-commits]

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@@ -808,6 +808,24 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
     }
     break;
   }
+  case ISD::SRL: {
+    // If we are only demanding sign bits then we can use the shift source
+    // directly.
+    if (std::optional<uint64_t> MaxSA =
+            DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1)) {
+      SDValue Op0 = Op.getOperand(0);
+      unsigned ShAmt = *MaxSA;
+      unsigned NumSignBits =
+          DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
+      unsigned LoDemandedBits = DemandedBits.countr_zero();
+      unsigned HiDemandedBits = DemandedBits.countl_zero();
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RKSimon wrote:

Sure - they were original LoBoundDemandedBits but that caused clang-format wrapping :) 

https://github.com/llvm/llvm-project/pull/114389