[llvm] [RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (PR #114317)

[Min-Yih Hsu via llvm-commits]

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@@ -4454,21 +4454,22 @@ class VPatTernaryNoMaskWithPolicy<string intrinsic,
                                   ValueType result_type,
                                   ValueType op1_type,
                                   ValueType op2_type,
-                                  int sew,
+                                  int log2sew,
                                   LMULInfo vlmul,
                                   VReg result_reg_class,
                                   RegisterClass op1_reg_class,
-                                  DAGOperand op2_kind> :
+                                  DAGOperand op2_kind,
+                                  bit sew_aware = false> :
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mshockwave wrote:

Fixed.

https://github.com/llvm/llvm-project/pull/114317