[llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)
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Wed Oct 30 09:57:17 PDT 2024
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git-clang-format --diff 49277253f016268e4a10109f1db2e53c60d35881 f7e1173f4e6d04cb5b8c76341b8537bf1859312d --extensions cpp -- llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp llvm/utils/TableGen/Common/CodeGenRegisters.cpp llvm/utils/TableGen/RegisterInfoEmitter.cpp
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diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 1ef75c6e02..3e10cc67b2 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -473,8 +473,7 @@ static SmallVector<MCPhysReg> ReservedHi = {
AArch64::W20_HI, AArch64::W21_HI, AArch64::W22_HI, AArch64::W23_HI,
AArch64::W24_HI, AArch64::W25_HI, AArch64::W26_HI, AArch64::W27_HI,
AArch64::W28_HI, AArch64::W29_HI, AArch64::W30_HI, AArch64::WSP_HI,
- AArch64::WZR_HI
- };
+ AArch64::WZR_HI};
BitVector
AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
diff --git a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
index 6ee64475f0..97b125df79 100644
--- a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
@@ -1,7 +1,7 @@
+#include "AArch64RegisterInfo.h"
#include "AArch64InstrInfo.h"
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
-#include "AArch64RegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
@@ -52,76 +52,76 @@ TEST(AArch64LaneBitmasks, SubRegs) {
// Test that the lane masks for the subregisters 'bsub, hsub, ssub, etc'
// are composed correctly.
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::bsub) |
- TRI.getSubRegIndexLaneMask(AArch64::bsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::bsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::hsub));
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::hsub) |
- TRI.getSubRegIndexLaneMask(AArch64::hsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::hsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::ssub));
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::ssub) |
- TRI.getSubRegIndexLaneMask(AArch64::ssub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::ssub_hi),
TRI.getSubRegIndexLaneMask(AArch64::dsub));
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub) |
- TRI.getSubRegIndexLaneMask(AArch64::dsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::dsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::zsub));
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub) |
- TRI.getSubRegIndexLaneMask(AArch64::zsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::zsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::zsub0));
// Test that the lane masks for tuples are composed correctly.
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub) |
- TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub));
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub) |
- TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub));
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub) |
- TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub_hi),
TRI.getSubRegIndexLaneMask(AArch64::dsub1));
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1) |
- TRI.getSubRegIndexLaneMask(AArch64::qsub1_then_dsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::qsub1_then_dsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::qsub1));
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sub_32) |
- TRI.getSubRegIndexLaneMask(AArch64::sub_32_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::sub_32_hi),
TRI.getSubRegIndexLaneMask(AArch64::sube64));
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32) |
- TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32_hi),
TRI.getSubRegIndexLaneMask(AArch64::subo64));
// Test that there is no overlap between different (sub)registers
// in a tuple.
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub0) &
- TRI.getSubRegIndexLaneMask(AArch64::dsub1) &
- TRI.getSubRegIndexLaneMask(AArch64::dsub2) &
- TRI.getSubRegIndexLaneMask(AArch64::dsub3),
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1) &
+ TRI.getSubRegIndexLaneMask(AArch64::dsub2) &
+ TRI.getSubRegIndexLaneMask(AArch64::dsub3),
LaneBitmask::getNone());
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::qsub0) &
- TRI.getSubRegIndexLaneMask(AArch64::qsub1) &
- TRI.getSubRegIndexLaneMask(AArch64::qsub2) &
- TRI.getSubRegIndexLaneMask(AArch64::qsub3),
+ TRI.getSubRegIndexLaneMask(AArch64::qsub1) &
+ TRI.getSubRegIndexLaneMask(AArch64::qsub2) &
+ TRI.getSubRegIndexLaneMask(AArch64::qsub3),
LaneBitmask::getNone());
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub0) &
- TRI.getSubRegIndexLaneMask(AArch64::zsub1) &
- TRI.getSubRegIndexLaneMask(AArch64::zsub2) &
- TRI.getSubRegIndexLaneMask(AArch64::zsub3),
+ TRI.getSubRegIndexLaneMask(AArch64::zsub1) &
+ TRI.getSubRegIndexLaneMask(AArch64::zsub2) &
+ TRI.getSubRegIndexLaneMask(AArch64::zsub3),
LaneBitmask::getNone());
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube32) &
- TRI.getSubRegIndexLaneMask(AArch64::subo32),
+ TRI.getSubRegIndexLaneMask(AArch64::subo32),
LaneBitmask::getNone());
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube64) &
- TRI.getSubRegIndexLaneMask(AArch64::subo64),
+ TRI.getSubRegIndexLaneMask(AArch64::subo64),
LaneBitmask::getNone());
// Test that getting a subregister results in the expected subregister.
@@ -132,9 +132,12 @@ TEST(AArch64LaneBitmasks, SubRegs) {
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub), AArch64::Q0);
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub0), AArch64::Z0);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_bsub), AArch64::B8);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_hsub), AArch64::H8);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_ssub), AArch64::S8);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_bsub),
+ AArch64::B8);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_hsub),
+ AArch64::H8);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_ssub),
+ AArch64::S8);
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1), AArch64::D8);
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::qsub1), AArch64::Q8);
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub1), AArch64::Z8);
@@ -142,7 +145,8 @@ TEST(AArch64LaneBitmasks, SubRegs) {
ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sube64), AArch64::X0);
ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64), AArch64::X1);
ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sub_32), AArch64::W0);
- ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64_then_sub_32), AArch64::W1);
+ ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64_then_sub_32),
+ AArch64::W1);
}
} // namespace
``````````
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https://github.com/llvm/llvm-project/pull/114263
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