[llvm] [RISCV] Support llvm.masked.expandload intrinsic (PR #101954)

[Luke Lau via llvm-commits]

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@@ -1359,6 +1359,10 @@ def TuneOptimizedZeroStrideLoad
                       "true", "Optimized (perform fewer memory operations)"
                       "zero-stride vector load">;
 
+def TuneOptimizedIndexedLoadStore
+   : SubtargetFeature<"optimized-indexed-load-store", "HasOptimizedIndexedLoadStore",
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lukel97 wrote:

I feel like I may have derailed this PR with my vluxeiN.v suggestion earlier, sorry. If we want to defer the decision about the subtarget feature till later I'm happy if we only do the vrgather.vv lowering in this PR. Especially given that according to my last review comment it does seem to be more performant than vluxeiN.v on the BPI F3

https://github.com/llvm/llvm-project/pull/101954