[llvm] [RISCV] Support llvm.masked.expandload intrinsic (PR #101954)

[Pengcheng Wang via llvm-commits]

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@@ -1359,6 +1359,10 @@ def TuneOptimizedZeroStrideLoad
                       "true", "Optimized (perform fewer memory operations)"
                       "zero-stride vector load">;
 
+def TuneOptimizedIndexedLoadStore
+   : SubtargetFeature<"optimized-indexed-load-store", "HasOptimizedIndexedLoadStore",
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wangpc-pp wrote:

I added a comment to explain it, do you think I should do more?

https://github.com/llvm/llvm-project/pull/101954