[llvm] [AArch64] Add ComputeNumSignBits for VASHR. (PR #113957)

[David Green via llvm-commits]

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@@ -3560,4 +3560,16 @@ entry:
   ret <4 x i16> %vrshrn_n1
 }
 
+define <8 x i16> @signbits_vashr(<8 x i16> %a)  {
+; CHECK-LABEL: signbits_vashr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshr.8h v0, v0, #8
+; CHECK-NEXT:    sshr.8h v0, v0, #9
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davemgreen wrote:

Yep, without the patch it would be 3 shifts. With it we realize that if you shift by a total of > bitwidth (or have signed bits > bitwidth), then the value is all-zero or all-one and shifting further doesn't alter the result.
I was trying to come up with a test - this one is a little artificial. This should help with some improvements to smull I was trying to make.

https://github.com/llvm/llvm-project/pull/113957