[llvm] [AArch64] Add ComputeNumSignBits for VASHR. (PR #113957)

[Sjoerd Meijer via llvm-commits]

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@@ -3560,4 +3560,16 @@ entry:
   ret <4 x i16> %vrshrn_n1
 }
 
+define <8 x i16> @signbits_vashr(<8 x i16> %a)  {
+; CHECK-LABEL: signbits_vashr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshr.8h v0, v0, #8
+; CHECK-NEXT:    sshr.8h v0, v0, #9
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sjoerdmeijer wrote:

Maybe you can quickly help me with this, I was expecting 3 shifts here, I guess that's the optimisation here but I don't see it.

https://github.com/llvm/llvm-project/pull/113957