[llvm] [LLVM][AArch64] Add assembly/disassembly for FTMOPA and BFTMOPA (PR #113230)

[via llvm-commits]

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@@ -387,6 +389,23 @@ static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
   return Success;
 }
 
+// Zk Is the name of the control vector register Z20-Z23 or Z28-Z31, encoded in
+// the "K:Zk" fields. Z20-Z23 = 000, 001,010, 011  and Z28-Z31 = 100, 101, 110,
+// 111
+static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                             const MCDisassembler *Decoder) {
+  // RegNo <  4 => Reg is in Z20-Z23 (offset 20)
+  // RegNo >= 4 => Reg is in Z28-Z31 (offset 24)
+  unsigned Reg = (RegNo < 4) ? (RegNo + 20) : (RegNo + 24);
+  if (!(Reg >= 20 && Reg <= 23) && !(Reg >= 28 && Reg <= 31))
+    return Fail;
+
+  unsigned Register =
+      AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);
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SpencerAbson wrote:

Good point, I have updated the Encoder/Decoder methods a little based on this.

https://github.com/llvm/llvm-project/pull/113230