[llvm] [LLVM][AArch64] Add assembly/disassembly of SVE BFSCALE instruction (PR #113168)

[via llvm-commits]

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@@ -0,0 +1,36 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-bfscale  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+bfscale z31.h, p7/m, z31.h, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfscale z31.h, p7/m, z31.h, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfscale z31.h, p7/m, z31.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfscale z31.h, p7/m, z31.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfscale z31.d, p7/m, z31.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfscale z31.d, p7/m, z31.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Predicate register out of range
+
+bfscale z31.h, p8/m, z31.h, z31.h
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SpencerAbson wrote:

Apologies - I should have specified that I meant a negative test, as using a zeroing predicate with `bfscale` should raise an error.

https://github.com/llvm/llvm-project/pull/113168