[llvm] [LLVM][AArch64] Add assembly/disassembly of SVE BFSCALE instruction (PR #113168)

[via llvm-commits]

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@@ -4163,7 +4163,9 @@ defm BFMIN_ZPZZ   : sve_fp_2op_p_zds_zeroing_bfloat<int_aarch64_sve_fmin>;
 defm BFMAX_ZPZZ   : sve_fp_2op_p_zds_zeroing_bfloat<int_aarch64_sve_fmax>;
 } // HasSVEB16B16, UseExperimentalZeroingPseudos
 
-
+let Predicates = [HasSVEBFSCALE] in {
+  def BFSCALE_ZPZZ : sve_fp_2op_p_zds_bfscale<0b1001, "bfscale", DestructiveBinaryComm>;
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Lukacma wrote:

Done

https://github.com/llvm/llvm-project/pull/113168