[llvm] [AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (PR #112403)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> The fix might be to spill one SGPR or reserve one ahead of time when allocating SGPRs for arguments.

We probably should just reserved a register always for these spill situations. The SGPR argument part is incidental 

https://github.com/llvm/llvm-project/pull/112403