[llvm] 0f3ed9c - [ARM] Use ARM::NoRegister in more places. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2024-10-18T17:39:21+01:00
New Revision: 0f3ed9c6505f5727712876c18ad71dba6271bc50

URL: https://github.com/llvm/llvm-project/commit/0f3ed9c6505f5727712876c18ad71dba6271bc50
DIFF: https://github.com/llvm/llvm-project/commit/0f3ed9c6505f5727712876c18ad71dba6271bc50.diff

LOG: [ARM] Use ARM::NoRegister in more places. NFC

Similar to #112507, this uses ARM::NoRegister in a few more places, as opposed
to the constant 0.

Added: 
    

Modified: 
    llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 54eb0118d77887..906519fef45db4 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2550,7 +2550,7 @@ class ARMOperand : public MCParsedAsmOperand {
     addVPTPredNOperands(Inst, N-1);
     MCRegister RegNum;
     if (getVPTPred() == ARMVCC::None) {
-      RegNum = MCRegister();
+      RegNum = ARM::NoRegister;
     } else {
       unsigned NextOpIndex = Inst.getNumOperands();
       auto &MCID = Parser->getInstrDesc(Inst.getOpcode());

diff  --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 814b71d1731988..38280adf2757b3 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -993,7 +993,7 @@ ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
     CCI = MI.insert(CCI, MCOperand::createImm(CC));
     ++CCI;
     if (CC == ARMCC::AL)
-      MI.insert(CCI, MCOperand::createReg(0));
+      MI.insert(CCI, MCOperand::createReg(ARM::NoRegister));
     else
       MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
   } else if (CC != ARMCC::AL) {
@@ -1060,7 +1060,7 @@ void ARMDisassembler::UpdateThumbVFPPredicate(
       I->setImm(CC);
       ++I;
       if (CC == ARMCC::AL)
-        I->setReg(0);
+        I->setReg(ARM::NoRegister);
       else
         I->setReg(ARM::CPSR);
       return;
@@ -1648,7 +1648,7 @@ static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
     Check(S, MCDisassembler::SoftFail);
   Inst.addOperand(MCOperand::createImm(Val));
   if (Val == ARMCC::AL) {
-    Inst.addOperand(MCOperand::createReg(0));
+    Inst.addOperand(MCOperand::createReg(ARM::NoRegister));
   } else
     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
   return S;
@@ -1660,7 +1660,7 @@ static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
   if (Val)
     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
   else
-    Inst.addOperand(MCOperand::createReg(0));
+    Inst.addOperand(MCOperand::createReg(ARM::NoRegister));
   return MCDisassembler::Success;
 }