[llvm] [TableGen] Added submulticlass typechecking to template arg values. (PR #112904)
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Fri Oct 18 07:11:03 PDT 2024
https://github.com/jofrn created https://github.com/llvm/llvm-project/pull/112904
Some typechecking was missing when parsing a submulticlass reference. This adds it in and fixes any mistyped codes in .td files.
>From 07265ac3a1a4f9c281f5b6d19955ece089d04754 Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Fri, 18 Oct 2024 02:15:49 -0400
Subject: [PATCH] [TableGen] Added submulticlass typechecking to template arg
values.
Some typechecking was missing when parsing a submulticlass reference.
This adds it in and fixes any mistyped codes in .td files.
---
llvm/lib/TableGen/TGParser.cpp | 6 ++++++
llvm/lib/Target/AMDGPU/VOPInstructions.td | 4 ++--
llvm/lib/Target/ARM/ARMInstrMVE.td | 16 ++++++++--------
llvm/lib/Target/ARM/ARMInstrNEON.td | 2 +-
llvm/test/TableGen/submulticlass-typecheck.td | 12 ++++++++++++
5 files changed, 29 insertions(+), 11 deletions(-)
create mode 100644 llvm/test/TableGen/submulticlass-typecheck.td
diff --git a/llvm/lib/TableGen/TGParser.cpp b/llvm/lib/TableGen/TGParser.cpp
index aed4f3fe0e96b5..de613f4f548395 100644
--- a/llvm/lib/TableGen/TGParser.cpp
+++ b/llvm/lib/TableGen/TGParser.cpp
@@ -812,6 +812,12 @@ ParseSubMultiClassReference(MultiClass *CurMC) {
return Result;
}
+ if (CheckTemplateArgValues(Result.TemplateArgs, Result.RefRange.Start,
+ &Result.MC->Rec)) {
+ Result.MC = nullptr; // Error checking value list.
+ return Result;
+ }
+
Result.RefRange.End = Lex.getLoc();
return Result;
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index 05a7d907d237ae..3ccf78cc57b43f 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -37,7 +37,7 @@ defvar VOPDX_Max_Index = 12;
class VOPD_Component<bits<5> OpIn, string vOPDName> {
Instruction BaseVOP = !cast<Instruction>(NAME);
- string VOPDName = "v_dual_" # !substr(vOPDName, 2);
+ string VOPDName = "v_dual_" # !if(!le(!size(vOPDName), 2), "", !substr(vOPDName, 2));
bits<5> VOPDOp = OpIn;
bit CanBeVOPDX = !le(VOPDOp, VOPDX_Max_Index);
}
@@ -1705,4 +1705,4 @@ def VOPTrue16Table : GenericTable {
let PrimaryKey = ["Opcode"];
let PrimaryKeyName = "getTrue16OpcodeHelper";
-}
\ No newline at end of file
+}
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 12c3968b9cecea..c3c4963a5da288 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -1998,7 +1998,7 @@ class MVE_VQxDMULH_Base<string iname, string suffix, bits<2> size, bit rounding,
def MVEvqdmulh : SDNode<"ARMISD::VQDMULH", SDTIntBinOp>;
multiclass MVE_VQxDMULH_m<string iname, MVEVectorVTInfo VTI,
- SDNode Op, Intrinsic unpred_int, Intrinsic pred_int,
+ SDPatternOperator Op, Intrinsic unpred_int, Intrinsic pred_int,
bit rounding> {
def "" : MVE_VQxDMULH_Base<iname, VTI.Suffix, VTI.Size, rounding>;
defvar Inst = !cast<Instruction>(NAME);
@@ -2199,7 +2199,7 @@ def subnsw : PatFrag<(ops node:$lhs, node:$rhs),
}]>;
multiclass MVE_VRHADD_m<MVEVectorVTInfo VTI, SDNode Op,
- SDNode unpred_op, Intrinsic PredInt> {
+ DefaultAttrsIntrinsic unpred_op, Intrinsic PredInt> {
def "" : MVE_VRHADD_Base<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? (i32 VTI.Unsigned)), !cast<Instruction>(NAME)>;
@@ -2303,7 +2303,7 @@ class MVE_VHSUB_<string suffix, bit U, bits<2> size,
: MVE_VHADDSUB<"vhsub", suffix, U, 0b1, size, pattern>;
multiclass MVE_VHADD_m<MVEVectorVTInfo VTI, SDNode Op,
- SDNode unpred_op, Intrinsic PredInt, PatFrag add_op,
+ DefaultAttrsIntrinsic unpred_op, Intrinsic PredInt, PatFrag add_op,
SDNode shift_op> {
def "" : MVE_VHADD_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
@@ -2335,7 +2335,7 @@ defm MVE_VHADDu16 : MVE_VHADD<MVE_v8u16, avgflooru, addnuw, ARMvshruImm>;
defm MVE_VHADDu32 : MVE_VHADD<MVE_v4u32, avgflooru, addnuw, ARMvshruImm>;
multiclass MVE_VHSUB_m<MVEVectorVTInfo VTI,
- SDNode unpred_op, Intrinsic pred_int, PatFrag sub_op,
+ DefaultAttrsIntrinsic unpred_op, Intrinsic pred_int, PatFrag sub_op,
SDNode shift_op> {
def "" : MVE_VHSUB_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
@@ -4794,7 +4794,7 @@ class MVE_VxMULH<string iname, string suffix, bit U, bits<2> size, bit round,
let validForTailPredication = 1;
}
-multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI, SDNode unpred_op,
+multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI, DefaultAttrsIntrinsic unpred_op,
Intrinsic PredInt, bit round> {
def "" : MVE_VxMULH<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, round>;
defvar Inst = !cast<Instruction>(NAME);
@@ -5370,8 +5370,8 @@ class MVE_VxADDSUB_qr<string iname, string suffix,
let validForTailPredication = 1;
}
-multiclass MVE_VHADDSUB_qr_m<string iname, MVEVectorVTInfo VTI, bit subtract, SDNode Op,
- Intrinsic unpred_int, Intrinsic pred_int, PatFrag add_op, PatFrag shift_op> {
+multiclass MVE_VHADDSUB_qr_m<string iname, MVEVectorVTInfo VTI, bit subtract, SDPatternOperator Op,
+ Intrinsic unpred_int, Intrinsic pred_int, PatFrag add_op, SDNode shift_op> {
def "" : MVE_VxADDSUB_qr<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, subtract, VTI.Size>;
defm : MVE_TwoOpPatternDup<VTI, Op, pred_int, (? (i32 VTI.Unsigned)), !cast<Instruction>(NAME)>;
defm : MVE_vec_scalar_int_pat_m<!cast<Instruction>(NAME),
@@ -5576,7 +5576,7 @@ class MVE_VxxMUL_qr<string iname, string suffix,
}
multiclass MVE_VxxMUL_qr_m<string iname, MVEVectorVTInfo VTI, bit bit_28,
- PatFrag Op, Intrinsic int_unpred, Intrinsic int_pred> {
+ SDPatternOperator Op, Intrinsic int_unpred, Intrinsic int_pred> {
def "" : MVE_VxxMUL_qr<iname, VTI.Suffix, bit_28, VTI.Size, VTI.Size>;
let Predicates = [HasMVEInt] in {
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index 48dcbdb137123a..20c52206fd3cd6 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -4906,7 +4906,7 @@ let Predicates = [HasMatMulInt8] in {
}
multiclass SUDOTLane<bit Q, RegisterClass RegTy, ValueType AccumTy, ValueType InputTy, dag RHS>
- : N3VMixedDotLane<Q, 1, "vsudot", "u8", RegTy, AccumTy, InputTy, null_frag, null_frag> {
+ : N3VMixedDotLane<Q, 1, "vsudot", "u8", RegTy, AccumTy, InputTy, null_frag, (ins)> {
def : Pat<
(AccumTy (int_arm_neon_usdot (AccumTy RegTy:$Vd),
(InputTy (bitconvert (AccumTy
diff --git a/llvm/test/TableGen/submulticlass-typecheck.td b/llvm/test/TableGen/submulticlass-typecheck.td
new file mode 100644
index 00000000000000..2a1f7ab094f881
--- /dev/null
+++ b/llvm/test/TableGen/submulticlass-typecheck.td
@@ -0,0 +1,12 @@
+// RUN: not llvm-tblgen %s 2>&1 | FileCheck %s
+// XFAIL: vg_leak
+// CHECK: {{.*}}: error: Value specified for template argument 'B::op' is of type bits<4>; expected type bits<8>: C::op
+// CHECK-NEXT: multiclass C<bits<4> op> : B<op>;
+class A<bits<8> op> {
+ bits<8> f = op;
+}
+multiclass B<bits<8> op> {
+ def : A<op>;
+}
+multiclass C<bits<4> op> : B<op>;
+defm D : C<0>;
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